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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DESCRIPTION
The M37736MHBXXXGP is a single-chip microcomputer using the 7700 Family core. This single-chip microcomputer has a CPU and a bus interface unit. The CPU is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. This microcomputer also includes a 32 kHz oscillation circuit, in addition to the ROM, RAM, multiple-function timers, serial I/O, A-D converter, and others. In the M37736MHBXXXGP, as the multiplex method of the external bus, either of 2 types can be selected.
qInterrupts ............................................................ 19 types, 7 levels qMultiple-function 16-bit timer ................................................. 5 + 3 qSerial I/O (UART or clock synchronous) ..................................... 3 q10-bit A-D converter ............................................ 8-channel inputs q12-bit watchdog timer qProgrammable input/output, output (ports P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10)..........................84 qClock generating circuit ........................................ 2 circuits built-in qPackage .........................................................................100-pin QFP
APPLICATION FEATURES
qNumber of basic instructions .................................................. 103 qMemory size ROM ............................................... 124 Kbytes RAM ................................................ 3968 bytes qInstruction execution time The fastest instruction at 25 MHz frequency ...................... 160 ns qSingle power supply ...................................................... 5 V 10% qLow power dissipation (at 25 MHz frequency) ............................................47.5 mW (Typ.) Control devices for general commercial equipment such as office automation, office equipment, and others. Control devices for general industrial equipment such as communication equipment, and others.
PIN CONFIGURATION (TOP VIEW)
80 P87/TXD1 79 P90/CTS2 78 P91/CLK2 77 P92/RXD2 76 P93/TXD2 75 P94 74 P95 73 P96 72 P97 71 P00/A0/CS0 70 P01/A1/CS1 69 P02/A2/CS2 68 P03/A3/CS3 67 P04/A4/CS4 66 P05/A5/RSMP 65 P06/A6/A16 64 P07/A7/A17 63 P10/A8/D8 62 P11/A9/D9 61 P12/A10/D10 60 P13/A11/D11 59 P14/A12/D12 58 P15/A13/D13 57 P16/A14/D14 56 P17/A15/D15 55 P20/A16/A0/D0 54 P21/A17/A1/D1 53 P22/A18/A2/D2 52 P23/A19/A3/D3 51 P24/A20/A4/D4
P86/RXD1 81 P85/CLK1 82 P84/CTS1/RTS1 83 P83/TXD0 84 P82/RXD0/CLKS0 85 P81/CLK0 86 P80/CTS0/RTS0/CLKS1 87 88 VCC AVCC 89 VREF 90 91 AVSS 92 VSS P77/AN7/XCIN 93 P76/AN6/XCOUT 94 P75/AN5/ADTRG 95 P74/AN4 96 P73/AN3 97 P72/AN2 98 P71/AN1 99 P70/AN0 100
M37736MHBXXXGP
50 P25/A21/A5/D5 49 P26/A22/A6/D6 48 P27/A23/A7/D7 47 P30/R/W/WEL 46 P31/BHE/WEH 45 P32/ALE 44 P33/HLDA 43 EVL0 42 EVL1 VCC 41 40 VSS 39 E/RDE 38 XOUT 37 XIN 36 RESET 35 BSEL 34 CNVSS 33 BYTE 32 P40/HOLD 31 P41/RDY
P67/TB2IN/f SUB 1 P66/TB1IN 2 P65/TB0IN 3 P64/INT2 4 P63/INT1 5 P62/INT0 6 P61/TA4IN 7 P60/TA4OUT 8 P57/TA3IN 9 P56/TA3OUT 10 P55/TA2IN 11 P54/TA2OUT 12 P53/TA1IN 13 P52/TA1OUT 14 P51/TA0IN 15 P50/TA0OUT 16 P107/KI3 17 P106/KI2 18 P105/KI1 19 P104/KI0 20 P103 21 P102 22 P101 23 P100 24 P47 25 P46 26 P45 27 P44 28 P43 29 P42/f1 30
Outline 100P6S-A
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Input/Output port P10
Output port P9

Reference External data bus width selection input voltage input BYTE VREF
Data Buffer DBH(8) Data Buffer DBL(8) Data Bus(Even) Data Bus(Odd)
Instruction Register(8)
Instruction Queue Buffer Q0(8) Instruction Queue Buffer Q1(8) Instruction Queue Buffer Q2(8)
P0(8)
P10(8)
P9(8)
AVCC
Incrementer(24)
Program Address Register PA(24) Data Address Register DA(24)
A-D Converter(10)
(0V) AVSS
P2(8)
Address Bus
CNVSS
Program Counter PC(16)
(0V) VSS
Program Bank Register PG(8)
Watchdog Timer
Timer TB2(16)
Timer TB1(16)
Timer TB0(16)
P4(8)
Incrementer/Decrementer(24)
VCC
Data Bank Register DT((8)
Bus method Reset input selection input RESET BSEL
Input Buffer Register IB(16)
Timer TA4(16)
Timer TA3(16)
Timer TA2(16)
Timer TA1(16)
Timer TA0(16)
Processor Status Register PS(11) Direct Page Register DPR(16)
M37736MHBXXXGP BLOCK DIAGRAM
XCOUT
Enable output E
XCIN
Stack Pointer S(16) Index Register Y(16)
RAM 3968 bytes
Index Register X(16)
Clock Generating Circuit
Accumulator B(16) Accumulator A(16)
Clock output XOUT
XCIN XCOUT
Clock input XIN
Arithmetic Logic Unit(16)
2
Input/Output port P8
ROM 124 Kbytes
P8(8)
Input/Output port P7
P7(8)
Input/Output port P6
P6(8)
Input/Output port P5
P5(8)
Input/Output port P4
UART2(9)
UART1(9)
UART0(9)
Input/Output port P3
P3(4)
Input/Output port P2
Input/Output port P1
P1(8)
Input/Output port P0
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FUNCTIONS OF M37736MHBXXXGP
Parameter Number of basic instructions Instruction execution time Memory size Input/Output ports Output port Multi-function timers Serial I/O A-D converter Watchdog timer Interrupts Clock generating circuit Supply voltage Power dissipation Input/Output characteristic Memory expansion Operating temperature range Device structure Package Input/Output voltage Output current ROM RAM P0 - P2, P4 - P8, P10 P3 P9 TA0, TA1, TA2, TA3, TA4 TB0, TB1, TB2 Functions 103 160 ns (the fastest instruction at external clock 25 MHz frequency) 124 Kbytes 3968 bytes 8-bit ! 9 4-bit ! 1 8-bit ! 1 16-bit ! 5 16-bit ! 3 (UART or clock synchronous serial I/O) ! 3 10-bit ! 1 (8 channels) 12-bit ! 1 3 external types, 16 internal types Each interrupt can be set to the priority level (0 - 7.) 2 circuits built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) 5 V 10% 47.5 mW (at external clock 25 MHz frequency) 5V 5 mA External bus mode A; maximum 16 Mbytes, External bus mode B; maximum 1 Mbytes -20 to 85 C CMOS high-performance silicon gate process 100-pin plastic molded QFP (100P6S-A)
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin Vcc, Vss CNVss
_____
Name Input/Output Power source Apply 5 V 10% to Vcc and 0 V to Vss. CNVss input Reset input Clock input Clock output Enable output Input Input Input Output Output
Functions
RESET
XIN XOUT
_
E
BYTE
BSEL
External data bus width selection input Bus method select input Analog power source input Reference voltage input I/O port P0
Input
Input
AVcc, AVss VREF P00 - P07
This pin controls the processor mode. Connect to Vss for the single-chip mode and the memory expansion mode, and to Vcc for the microprocessor mode. When "L" level is applied to this pin, the microcomputer enters the reset state. These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartzcrystal oscillator between XIN and XOUT. When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open. This pin functions as the enable signal output pin which indicates the access status in the internal bus. In the external bus mode B and the memory expansion mode or the microprocessor mode, ___ this pin output signal RDE. In the memory expansion mode or the microprocessor mode, this pin determines whether the external data bus has an 8-bit width or a 16-bit width. The data bus has a 16-bit width when "L" signal is input and an 8-bit width when "H" signal is input. In the memory expansion mode or the microprocessor mode, this pin determines the external bus mode. The bus mode becomes the external bus mode A when "H" signal is input, and the external bus mode B when "L" signal is input. Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss. This is reference voltage input pin for the A-D converter. In the single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register is available so that each pin can be programmed for input or output. These ports are in the input mode when reset. In the memory expansion mode or the microprocessor mode, these pins output address (A0 - A7) ____ ___ ___ at the external bus mode A, and these pins output signals CS0 - CS4 and RSMP, and addresses (A16, A17) at the external bus mode B. In the single-chip mode, these pins have the same functions as port P0. When the BYTE pin is set to "L" in the memory expansion mode or the microprocessor mode and external data bus has a 16-bit width, high-order data (D8 - D15) is input/output or an address (A8 - A15) is output. When the BYTE pin is "H" and an external data bus has an 8-bit width, only address (A8 - A15) is output. In the single-chip mode, these pins have the same functions as port P0. In the memory expansion mode or the microprocessor mode, low-order data (D0 - D7) is input/output or an address is output. When using the external bus mode A, the address is A16 - A23. When using the external bus mode B, the address is A0 - A7. In the single-chip mode, these pins have ___same function as port P0. In the memory expansion __ the ____ mode or the microprocessor mode, R/W, BHE, ALE, and HLDA signals are output at the external ___ ___ ____ bus mode A, and WEL, WEH, ALE, and HLDA signals are output at the external bus mode B. In the single-chip mode, these pins have the same functions as port P0. In the memory expansion ____ ___ mode or the microprocessor mode, P40, P41 and P42 become HOLD and RDY input pins, and a clock 1 output pin, respectively. Functions of the other pins are the same as in the single-chip mode. However, in the memory expansion mode, P42 can be selected as an I/O port. In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timers A0 to A3. In addition to having the same functions as port P0 in the single-chip mode, these pins also ___ ___ function as I/O pins for timer A4, input pins for external interrupt input (INT0 - INT2) and input pins for timers B0 to B2. P67 also functions as sub-clock SUB output pin. In addition to having the same functions as port P0 in the single-chip mode, these pins function as input pins for A-D converter. Additionally, P76 and P77 have the function as the output pin (XCOUT) and the input pin (XCIN) of the sub-clock (32 kHz) oscillation circuit, respectively. When P76 and P77 are used as the XCOUT and XCIN pins, connect a resonator or an oscillator between the both. In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for UART 0 and UART 1. Port P9 is an 8-bit I/O port. These ports are floating when reset. When writting to the port latch, these ports become the output mode. P90 - P93 also function as I/O port for UART 2. In addition to having the same functions as port P0 in the single-chip mode, P104 - P107 also __ __ function as input pins for key input interrupt input (KI0 - KI3). These pins should be left open.
Input I/O
P10 - P17
I/O port P1
I/O
P20 - P27
I/O port P2
I/O
P30 - P33
I/O port P3
I/O
P40 - P47
I/O port P4
I/O
P50 - P57 P60 - P67
I/O port P5 I/O port P6
I/O I/O
P70 - P77
I/O port P7
I/O
P80 - P87
I/O port P8
I/O Output I/O Output
P90 - P97 Output port P9 P100 - P107 I/O port P10 EVL0, EVL1 --
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
The M37736MHBXXXGP contains the following peripheral devices on a single chip: ROM, RAM, CPU, bus interface unit, timers, serial I/O, A-D converter, I/O ports, clock generating circuit and others. Each of these devices is described below.
MEMORY
The memory map is shown in Figure 1. The address space has a capacity of 16 Mbytes and is allocated to addresses from 016 to FFFFFF16. The address space is divided by 64-Kbyte unit called bank. The banks are numbered from 016 to FF16. However, in the external bus mode B, banks 1016 to FF16 cannot be accessed. Built-in ROM, RAM and control registers for internal peripheral devices are assigned to banks 016 and 116. The 124-Kbyte area from addresses 100016 to 1FFFF16 is the built-in ROM. Addresses FFD616 to FFFF16 are the RESET and interrupt vector addresses and contain the interrupt vectors. Refer to the section on interrupts for details.
The 3968-byte area allocated to addresses from 8016 to FFF16 is the built-in RAM. In addition to storing data, the RAM is used as stack during a subroutine call or interrupts. Peripheral devices such as I/O ports, A-D converter, serial I/O, timer, and interrupt control registers are allocated to addresses from 016 to 7F16. Additionally, the internal ROM and RAM area can be modified by software. Refer to the section on ROM area modification function for details. A 256-byte direct page area can be allocated anywhere in bank 016 by using the direct page register (DPR). In the direct page addressing mode, the memory in the direct page area can be accessed with two words. Hence program steps can be reduced.
00000016 Bank 016 00FFFF16 01000016
00000016 00007F16 00008016 Internal RAM 3968 bytes
00000016 Internal peripheral devices control registers
refer to Fig. 2 for detail information
00007F16 000FFF16 00100016 Interrupt vector table 00FFD616
A-D/UART2 trans./rece.
Bank 116
01FFFF16
*******************
UART1 transmission UART1 receive UART0 transmission UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0
INT2/Key input INT1
Internal ROM 124 Kbytes 00FFD616 00FFFF16 FE000016
Bank FE16 FEFFFF16 FF000016 Bank FF16 FFFFFF16 01FFFF16 00FFFE16
INT0
Watchdog timer
DBC
BRK instruction Zero divide
RESET
Notes 1. Internal ROM and RAM area can be modified. (Refer to the section on ROM area modification function.) 2. In the external bus mode B, banks 1016 to FF16 cannot be accessed. Fig. 1 Memory map
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address (Hexadecimal notation) 000000 000001 000002 Port P0 register 000003 Port P1 register 000004 Port P0 direction register 000005 Port P1 direction register 000006 Port P2 register 000007 Port P3 register 000008 Port P2 direction register 000009 Port P3 direction register 00000A Port P4 register 00000B Port P5 register 00000C Port P4 direction register 00000D Port P5 direction register 00000E Port P6 register 00000F Port P7 register 000010 Port P6 direction register 000011 Port P7 direction register 000012 Port P8 register 000013 Port P9 register 000014 Port P8 direction register 000015 000016 Port P10 register 000017 000018 Port P10 direction register 000019 00001A 00001B 00001C Reserved area (Note) 00001D Reserved area (Note) 00001E A-D control register 0 00001F A-D control register 1 000020 A-D register 0 000021 000022 A-D register 1 000023 000024 A-D register 2 000025 000026 A-D register 3 000027 000028 A-D register 4 000029 00002A A-D register 5 00002B 00002C A-D register 6 00002D 00002E A-D register 7 00002F 000030 UART 0 transmit/receive mode register 000031 UART 0 baud rate register (BRG0) 000032 UART 0 transmission buffer register 000033 000034 UART 0 transmit/receive control register 0 000035 UART 0 transmit/receive control register 1 000036 UART 0 receive buffer register 000037 000038 UART 1 transmit/receive mode register 000039 UART 1 baud rate register (BRG1) 00003A UART 1 transmission buffer register 00003B 00003C UART 1 transmit/receive control register 0 00003D UART 1 transmit/receive control register 1 00003E UART 1 receive buffer register 00003F
Address (Hexadecimal notation) 000040 000041 000042 000043 000044 000045 000046 000047 000048 000049 00004A 00004B 00004C 00004D 00004E 00004F 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005A 00005B 00005C 00005D 00005E 00005F 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006A 00006B 00006C 00006D 00006E 00006F 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007A 00007B 00007C 00007D 00007E 00007F
Count start flag One-shot start flag Up-down flag
Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Watchdog timer register Watchdog timer frequency selection flag Reserved area (Note) Memory allocation control register UART 2 transmit/receive mode register UART 2 baud rate register (BRG2) UART 2 transmission buffer register UART 2 transmit/receive control register 0 UART 2 transmit/receive control register 1 UART 2 receive buffer register Oscillation circuit control register 0 Port function control register Serial transmit control register Oscillation circuit control register 1 A-D/UART 2 trans./rece. interrupt control register UART 0 transmission interrupt control register UART 0 receive interrupt control register UART 1 transmission interrupt control register UART 1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2/Key input interrupt control register Note. Do not write to this address.
Fig. 2 Location of internal peripheral devices and interrupt control registers
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CENTRAL PROCESSING UNIT (CPU)
The CPU has ten registers and is shown in Figure 3. Each of these registers is described below.
Also, when executing a block transfer instruction (MVP, MVN), the contents of index register X indicates the low-order 16 bits of the source data address. The third byte of the MVP or MVN is the highorder 8 bits of the source data address.
ACCUMULATOR A (A)
Accumulator A is the main register of the microcomputer. It consists of 16 bits and the low-order 8 bits can be used separately. The data length flag (m) determines whether the register is used as a 16-bit register or as an 8-bit register. It is used as a 16-bit register when flag m is "0" and as an 8-bit register when flag m is "1". Flag m is a part of the processor status register (PS) which is described later. Data operations such as arithmetic operation, data transfer, input/ output, etc., are executed mainly through the accumulator A.
INDEX REGISTER Y (Y)
Index register Y consists of 16 bits and the low-order 8 bits can be used separately. The index register length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. It is used as a 16-bit register when flag x is "0" and as an 8-bit register when flag x is "1". Flag x is a part of the processor status register (PS) which is described later. In an index addressing mode where register Y is used as the index register, the contents of this address is added to obtain the real address. Also, when executing a block transfer instruction (MVP, MVN), the contents of index register Y indicates the low-order 16 bits of the destination data address. The second byte of the MVP or MVN is the high-order 8 bits of the destination data address.
ACCUMULATOR B (B)
Accumulator B has the same functions as accumulator A, but the use of accumulator B requires more instruction bytes and execution cycles than accumulator A.
INDEX REGISTER X (X)
Index register X consists of 16 bits and the low-order 8 bits can be used separately. The index register length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. It is used as a 16-bit register when flag x is "0" and as an 8-bit register when flag x is "1". Flag x is a part of the processor status register (PS) which is described later. In an index addressing mode where register X is used as the index register, the contents of this address is added to obtain the real address.
15
7
0
AH
15 7
AL
0
Accumulator A (A) Accumulator B (B)
0
BH
15 7
BL XL
7 0
XH
15
Index register X (X) Index register Y (Y)
0
YH
15
YL S
Stack pointer (S)
0
7
0
15
PG
7 0
Program bank register (PG)
15
PC
0
Program counter (PC) Direct page register (DPR)
0
DT
Data bank register (DT)
15
DPR
7
IPL2 IPL1 IPL0
00000
NVmxD I Z C
Processor status register (PS) Carry flag Zero frag Interrupt disable flag Decimal mode flag Index register length flag Data length flag Overflow flag Negative flag Processor interrupt priority level (IPL)
Fig. 3 Register structure
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
STACK POINTER (S)
Stack pointer (S) is a 16-bit register. It is used during a subroutine call or interrupts. It is also used during stack, stack pointer relative, or stack pointer relative indirect indexed Y addressing modes.
1. Carry flag (C)
The carry flag contains the carry or borrow generated by the ALU after an arithmetic operation. This flag is also affected by shift or rotate instruction. This flag can be set or reset directly with the SEC, CLC instructions or with the SEP, CLP instructions.
PROGRAM COUNTER (PC)
Program counter (PC) is a 16-bit counter that indicates the low-order 16 bits of the next program memory address to be executed. There is a bus interface unit between the program memory and the CPU, so that the program memory is accessed through the bus interface unit. This is described later.
2. Zero flag (Z)
This zero flag is set when the result of an arithmetic operation or data transfer is zero and reset when it is not. This flag can be set or reset directly with the SEP or CLP instruction.
PROGRAM BANK REGISTER (PG)
Program bank register (PG) is an 8-bit register that indicates the highorder 8 bits of the next program memory address to be executed. When a carry occurs by incrementing the contents of the program counter, the contents of the program bank register (PG) is incremented by 1. Also, when a carry or borrow occurs after adding or subtracting the offset value to or from the contents of the program counter (PC) by using a branch instruction, the contents of the program bank register (PG) is incremented or decremented by 1 so that programs can be written without worrying about bank boundaries.
3. Interrupt disable flag ( I )
When the interrupt disable flag is "1", all interrupts except watchdog ____ timer, DBC, and software interrupt are disabled. This flag is automatically set to "1" when an interrupt is accepted. It can be set or reset directly with the SEI, CLI instructions or SEP and CLP instructions.
4. Decimal mode flag (D)
The decimal mode flag determines whether addition and subtraction are performed in the binary or the decimal system. Binary arithmetic is performed when this flag is "0". If it is "1", decimal arithmetic is performed with each word treated as the 2- or 4-digit number. Arithmetic operation is performed with 4-digit number when the data length flag (m) is "0" and with 2-digit number when it is "1". Decimal correction is automatically performed. (Decimal operation is possible only with the ADC and SBC instructions.) This flag can be set or reset with the SEP or CLP instruction.
DATA BANK REGISTER (DT)
Data bank register (DT) is an 8-bit register. With some addressing modes, a part of the data bank register (DT) is used to specify a memory address. The contents of data bank register (DT) is used as the high-order 8 bits of a 24-bit address. Addressing modes that use the data bank register (DT) to specify the address are direct indirect, direct indexed X indirect, direct indirect indexed Y, absolute, absolute bit, absolute indexed X, absolute indexed Y, absolute bit relative, and stack pointer relative indirect indexed Y.
5. Index register length flag (x)
The index register length flag determines whether index register X and index register Y are used as 16-bit registers or as 8-bit registers. The registers are used as 16-bit registers when flag x is "0" and as 8bit registers when it is "1". This flag can be set or reset with the SEP or CLP instruction.
DIRECT PAGE REGISTER (DPR)
Direct page register (DPR) is a 16-bit register. Its contents is used as the base address of a 256-byte direct page area. The direct page area is allocated in bank 016, but when the contents of DPR is FF0116 or more, the direct page area spans across bank 016 and bank 116. All direct addressing modes use the contents of the direct page register (DPR) to generate the data address. When the low-order 8 bits' contents of the direct page register (DPR) is "0016", the number of cycles required to generate an address is minimized. Hence the loworder 8 bits' contents of the direct page register (DPR) is usually set to "0016".
6. Data length flag (m)
The data length flag determines whether the data has a length of 16 bits or that of 8 bits. The 16-bit length is selected when flag m is "0" and the 8-bit length is selected when it is "1". This flag can be set or reset with the SEM, CLM instructions or with the SEP, CLP instructions.
PROCESSOR STATUS REGISTER (PS)
Processor status register (PS) is an 11-bit register. It consists of flags which indicate the result of operation and the processor interrupt priority level (IPL). Branch operations can be performed by testing flags C, Z , V, and N. The details of each processor status register bit are described below.
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7. Overflow flag (V)
The overflow flag is effective only when addition or subtraction is performed with treating a word as a signed binary number. When the data length flag (m) is "0", the overflow flag is set if the result of addition or subtraction is outside the range between - 32768 and +32767. When the data length flag (m) is "1", the overflow flag is set if the result of addition or subtraction is outside the range between -128 and +127. It is reset in the other cases. The overflow flag can also be set or reset directly with the SEP or CLV, CLP instructions.
9. Processor interrupt priority level (IPL)
The processor interrupt priority level (IPL) consists of 3 bits and determines the processor interrupt priority level (0 to 7). Interrupt is enabled when the interrupt priority level of the device requesting interrupt (the priority can be set using the interrupt control register) is higher than the processor interrupt priority level. When interrupt is enabled, the current processor interrupt priority level is saved in a stack and the processor interrupt priority level is replaced by the interrupt priority level of the device requesting the interrupt. Refer to the section on interrupts for more details.
8. Negative flag (N)
The negative flag is set when the result of arithmetic operation or data transfer is negative (If data length flag (m) is "0", data bit 15 is "1". If data length flag (m) is "1", data bit 7 is "1".) It is reset in the other cases. It can also be set or reset with the SEP or CLP instructions.
BUS INTERFACE UNIT
The CPU operates on an internal clock 's frequency. Internal clock 's frequency is twice the bus cycle frequency. In order to speed up processing, a bus interface unit is used to pre-fetch instructions when the data bus is idle. The bus interface unit synchronizes the CPU and the bus and pre-fetches instructions. Figure 4 shows the relationship between the CPU and the bus interface unit. The bus interface unit has a program address register, a 3-byte instruction queue buffer, a data address register, and a 2-byte data buffer. The bus interface unit obtains an instruction code from the memory and stores it in the instruction queue buffer, obtains data from the memory and stores it in the data buffer, or writes the data from the data buffer to the memory.
D'15 - D'8 D'7 - D'0 A'23 - A'0
D15 - D8 D7 - D0 A23 - A0
BHE
CPU
Bus interface unit
R/W
E
Control signal
ALE BYTE
HOLD
Fig. 4 Relationship between the CPU and the bus interface unit
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The bus interface unit operates using one of the waveforms (1) to (10) shown in Figure 5. The standard waveforms are (1) and (2). The ALE signal is used to latch only the address signal from the multiplexed signal containing data and address. _ Signal E becomes "L" when the bus interface unit reads an instruction code or data from the memory or when it writes data to the _ memory. Whether _ perform read or write is controlled by signal R/W. When to signal R/W is "H", read is performed; when "L", write is performed. _ _ In the external bus mode B, signals E and R/W are not directly output to the outside of the chip. In the memory expansion mode or the ___ ___ ____ microprocessor mode, read signal RDE and write_ signals WEL, WEH ___ are output to the outside of the chip. While signal E is "L", signal ___ RDE _ ___ becomes "L" at reading. While signal E is "L", signals WEL and WEH become "L" at writing.
Waveform (1) in Figure 5 is used to access a single byte or two bytes simultaneously. To read or write two bytes simultaneously, the first address accessed must be even. Furthermore, when accessing an external memory area in the memory expansion mode or the microprocessor mode, set the bus width selection input pin (BYTE) to "L" (external data bus has a width of 16 bits). The data bus in the internal memory area is always treated as the 16-bit bus independent of BYTE.
Internal clock
Internal clock A D
Port P2 (1)
E
Port P2 (7)
E
A
D
ALE Access time Port P2 (2)
E A D
A+1
ALE Access time
D
Port P2 (8)
E
A
D
A+1
D
ALE Access time Port P2 (3)
E A D
ALE Access time Port P2 (9)
E A D
A+1
D
ALE Access time Port P2 (4)
E A D
A+1
ALE Access time
D
Port P2 (10)
E
A
D
A+1
D
ALE Access time Port P2 (5)
E A D
A+1
ALE Access time
D
A : Address D : Data
_ ___
ALE Access time Port P2 (6)
E A D
A+1
While signal E is "L" in the external bus mode ___ B, signal ____ RDE becomes "L" (in the read cycle) or signals WEL and WEH become "L" (in the write cycle).
D
ALE Access time
Fig. 5 Bus access timing
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When performing 16-bit data read or write, waveform (2) is used to access each byte one by one if the conditions for simultaneously accessing two bytes are not satisfied. However, when prefetching the instruction code, if the address of the instruction code is odd, waveform (1) is used, and only one byte is read in the instruction queue buffer. ___ Access to the even/odd address is controlled by signals BHE and A0. ___ In the external bus mode B, signal BHE is not directly output to the ___ ___ outside of the chip. Write signals (WEL, WEH) are generated corresponding to the accessed address (even or odd). Bit 2 of processor mode register 0 (address 5E16) is the wait bit. When the external memory area is accessed in the memory expansion mode or the microprocessor mode with this bit set to "0", the width of _ signal E is extended and access time can be extended. There are two ways to extend the access time and they are selected with bit 0 of the processor mode register 1 (address 5F16). _ When this bit is set to "1", the "L" width of signal E in (1) becomes twice as long as in (3) and the access time becomes 1.5 times (wait _ 1). When this bit is set to "0", signals ALE and E in (1) are extended as in (7) and the access time is doubled (wait 0). However, these signals are not extended when accessing the internal memory area. When the wait bit is set to "1", these signals are not extended when accessing any memory area regardless of the bit 0 of the processor mode register 1. Waveforms (4), (5), and (6) show the entire waveform, first half, and last half respectively of waveform (2) for wait 1. Waveforms (8), (9), and (10) show the entire waveform, first half, and last half respectively of waveform (2) for wait 0. Instruction code read, data read, and data write are described below. Instruction code read will be described first. The CPU obtains instruction codes from the instruction queue buffer and executes them. The CPU notifies the bus interface unit that it is requesting an instruction code during an instruction code request cycle. If the requested instruction code is not yet stored in the instruction queue buffer, the bus interface unit halts the CPU until more instructions than requested is stored in the instruction queue buffer. Even if there is no instruction code request from the CPU, the bus interface unit reads instruction codes from the memory and stores them in the instruction queue buffer when the instruction queue buffer is empty or when only one instruction code is stored and the bus is idle on the next cycle. This is referred to as instruction pre-fetching. Normally , when reading an instruction code from the memory, if the accessed address is even, the next odd address is read together with the instruction code and stored in the instruction queue buffer. However, in the memory expansion mode or the microprocessor mode, only one byte is read and stored in the instruction queue buffer if the following conditions are satisfied. * The address to be read is in the external memory area when the external data bus has an 8-bit width (BYTE = "H"). * The address to be read is odd. Therefore, waveform (1), (3) or (7) in Figure 5 is used for instruction code read. Data read and write are described below.
The CPU notifies the bus interface unit when performing data read or write. At this time, the bus interface unit halts the CPU if the bus interface unit is already using the bus or if there is a request with higher priority. When data read or write is enabled, the bus interface unit uses one of the waveforms from (1) to (10) in Figure 5 to perform the operation. During data read, the CPU waits until the entire data is stored in the data buffer. The bus interface unit sends the address received from the CPU to the address bus. Then it reads the memory when signal _ E is "L" and stores the result in the data buffer. During data write, the CPU writes the data in the data buffer and the bus interface unit writes it to the memory . Therefore, the CPU can proceed to the next step without waiting for write completed. The bus interface unit sends the address received from the CPU to the address _ bus. Then when signal E is "L", the bus interface unit sends the data in the data buffer to the data bus and writes it to the memory.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
INTERRUPTS
Table 1 shows the interrupt sources and the corresponding interrupt vector addresses. Reset is also treated as a source of interrupt and is described in this section. ___ DBC is an interrupt used only for debugging. ___ Interrupts other than reset, DBC, watchdog timer, zero divide, and BRK instruction all have their respective interrupt control registers. Table 2 shows the addresses of the interrupt control registers and Figure 6 shows the bit configuration of the interrupt control register. The interrupt request bit is automatically cleared by hardware during reset or when processing an interrupt. Also, interrupt request bits ___ other than DBC and watchdog timer can be cleared by software. ___ ___ INT0 to INT2 are external interrupts, and whether to cause an interrupt at the input level (level sense) or at the edge (edge sense) can be selected with the level sense/edge sense selection bit. Furthermore, the polarity of the interrupt input can be selected with a polarity selection bit. ___ In the INT2 /Key input interrupt, whether to input an interrupt request ___ __ __ from the INT2 pin or the KI0 - KI3 pins can be selected by bit 7 of the port function control register (refer to Figure 11). Timer and UART interrupts are described in the respective section. The priority of interrupts when multiple interrupts are caused simultaneously is partially fixed by hardware, but it can also be adjusted by software as shown in Figure 7. The hardware priority is fixed as___ follows: reset > DBC > watchdog timer > other interrupts
Table 1. Interrupt sources and the interrupt vector addresses Interrupts A-D/UART2 trans./rece. UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 ___ INT2 /Key input ___
___
INT1 INT0
Watchdog timer ___ DBC (unusable) BRK instruction Zero divide Reset
Vector addresses 00FFD616 00FFD716 00FFD816 00FFD916 00FFDA16 00FFDB16 00FFDC16 00FFDD16 00FFDE16 00FFDF16 00FFE016 00FFE116 00FFE216 00FFE316 00FFE416 00FFE516 00FFE616 00FFE716 00FFE816 00FFE916 00FFEA16 00FFEB16 00FFEC16 00FFED16 00FFEE16 00FFEF16 00FFF016 00FFF116 00FFF216 00FFF316 00FFF416 00FFF516 00FFF616 00FFF716 00FFF816 00FFF916 00FFFA16 00FFFB16 00FFFC16 00FFFD16 00FFFE16 00FFFF16
76543210
Interrupt priority level selection bits Interrupt request bit 0 : No interrupt 1 : Interrupt Interrupt control register configuration for timers A0 to A4, timers B0 to B2, UART0, UART1 and A-D/UART2 trans./rece. 76543210
Interrupt priority level selection bits Interrupt request bit 0 : No interrupt 1 : Interrupt Polarity selection bit 0 : Interrupt request bit is set at "H" level for level sense or at the falling edge for edge sence. 1 : Interrupt request bit is set at "L" level for level sense or at the rising edge for edge sense. Level sense/edge sense selection bit 0 : Edge sense 1 : Level sense Interrupt control register configuration for INT0 to INT2/Key input Fig. 6 Interrupt control register bit configuration
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Table 2. Addresses of interrupt control registers Interrupt control registers A-D/UART2 trans./rece. interrput control register UART0 transmit interrput control register UART0 receive interrput control register UART1 transmit interrput control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register ___ INT0 interrupt control register ___ INT1 interrupt control register ___ INT2/Key input interrupt control register addresses 00007016 00007116 00007216 00007316 00007416 00007516 00007616 00007716 00007816 00007916 00007A16 00007B16 00007C16 00007D16 00007E16 00007F16
Because priority detection takes some time, no sampling pulse is generated for a certain interval even if it is the next operation code fetch cycle.
Priority is determined by hardware 4
3
Watchdog timer
2
DBC
1 Reset
A-D converter, UART, Timer, INT interrupts Priority can be changed by software inside 4 Fig. 7 Interrupt priority Level 0
Interrupts caused by a BRK instruction and when dividing by zero are software interrupts and are not included in this list. Other interrupts previously mentioned are A-D converter, UART, Timer, INT interrupts. The priority of these interrupts can be changed by changing the interrupt priority level selection bits of the corresponding interrupt control register with software. Figure 8 shows a diagram of the interrupt priority detection circuit. When an interrupt is caused, the each interrupt device compares its own priority with the priority from above and if its own priority is higher, then it sends the priority below and requests the interrupt. If the priorities are the same, the one above has priority. This comparison is repeated to select the interrupt with the highest priority among the interrupts that are being requested. Finally the selected interrupt is compared with the processor interrupt priority level (IPL) contained in the processor status register (PS), and the request is accepted if it is higher than IPL and the interrupt disable flag (I) is "0". The request is not accepted if flag I is "1". The reset, ___ DBC, and watchdog timer interrupts are not affected by the interrupt disable flag (I). When an interrupt is accepted, the contents of the processor status register (PS) is saved to the stack and the interrupt disable flag (I) is set to "1". Furthermore, the interrupt request bit of the accepted interrupt is cleared to "0" and the processor interrupt priority level (IPL) in the processor status register (PS) is replaced by the priority level of the accepted interrupt. Therefore, multiple interrupts are possible by resetting the interrupt disable flag (I) to "0" and enable further interrupts. ___ For reset, DBC, watchdog timer, zero divide, and BRK instruction interrupts, which do not have an interrupt control register, the processor interrupt level (IPL) is set as shown in Table 3. Priority detection is performed by latching the interrupt request bit and interrupt priority level selection bits so that they do not change. They are sampled at the first half and latched at the last half of the operation code fetch cycle.
A-D/UART2 trans./rece. Interrupt request UART1 transmit UART1 receive UART0 transmit Reset UART0 receive Timer B2 Timer B1
DBC
Timer B0 Timer A4 Timer A3
Watchdog timer
Timer A2 Timer A1
Interrupt disable flag(I)
Timer A0
INT2/Key input
IPL
INT1 INT0
Fig. 8 Interrupt priority detection circuit
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
As shown in Figure 9, there are three different interrupt priority detection time from which one is selected by software. After the selected time has elapsed, the interrupt which has the highest priority is determined and is processed after the current instruction execution has been completed. The time is selected with bits 4 and 5 of the processor mode register 0 (address 5E16) shown in Figure 10. Table 4 shows the relationship between these bits and the number of cycles. After a reset, the processor mode register 0 is initialized to "0016". Therefore, the longest time is selected. However, the shortest time should be selected by software.
Table 3. Value set in processor interrupt level (IPL) during an interrupt Interrupt types Setting value Reset 0 ___ DBC 7 Watchdog timer 7 Zero divide Not change value of IPL. BRK instruction Not change value of IPL.
Table 4. Relationship between interrupt priority detection time selection bits and number of cycles Interrupt priority detection time selection bits Number of cycles Bit 5 Bit 4 0 0 7 cycles of 0 1 4 cycles of 1 0 2 cycles of : internal clock
Internal clock Operation code fetch cycle Sampling pulse 0 1 2
Priority detection time Select one from 0 to 2 with bits 4 and 5 of the processor mode register 0
Fig. 9 Interrupt priority detection time
7
6 0
54
3
2
1
0
Address
Processor mode register 0 (5E16) Processor mode bits 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode Wait bit 0 : Wait 1 : No wait Software reset bit The processor is reset when this bit is set to "1". Interrupt priority detection time selection bits 0 0 : Select 0 in Figure 9 0 1 : Select 1 in Figure 9 1 0 : Select 2 in Figure 9 Always "0" Clock 1 output selection bit 0 : No 1 output 1 : 1 output
Fig. 10 Processor mode register 0 configuration
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___ __ __
By setting the port function control register, the INT2/Key input interrupt function __ be switched to the key input interrupt function which can __ uses the KI0 to KI3 inputs. Figure 11 shows the bit configuration of the ___ port function control register, and Figure 12 shows the INT2/Key input interrupt input circuit block diagram. When the key input interrupt selection bit of the port function control ___ ___ register is "0", a signal is input from the INT2 pin to the INT2 /Key input ___ interrupt control circuit and the INT2 interrupt is normally performed. When the __ input interrupt selection bit is "1", signals input from key __ the KI0 to KI3 pins are___ inverted, and then the logical sum of these signals is input to the INT2 interrupt control circuit. In this case, the __ __ external interrupt which uses the KI0 to KI3 pins is performed. (Pins __ __ KI0 to KI3 correspond to ports P104 to P107, respectively.) ___ Additionally, by setting the port P6 pull-up selection bit 1 to "1", the INT2 input is added to that logical sum, so that the external interrupt which uses __ __ ___ the inputs KI0 to KI3 and INT2 is performed. When using the key input interrupt, it is necessary to select the edge sense which uses the ___ falling edge by setting the INT2 /Key input interrupt control register. Because of this selection, a key input ___ interrupt request occurs when __ __ "L" is input to one of the KI0 to KI3 and INT2 pins. The interrupt vector ___ and the interrupt control register are common to the INT2 and key input interrupts.
Pull-up resistors (transistors) can be added to the KI0 to KI3 pins by setting "1" to the port P10 pull-up selection bit and "0" to the contents of the port P10i (i = 4 to___ 7) direction register. Similarly, a pull-up resistor can be added to the INT2 pin by setting "1" to the port P6 pull-up selection bit 1 and "0" to the content of the port P64 direction register. With the key input interrupt and the pull-up function, the key input circuit is easily composed.
Port P6 pull-up selection bit 1
Pull-up transistor P64/INT2
Port P64 direction register
INT2/Key input interrupt control register
(Address 7F16)
Port P6 pull-up selection bit 1 Port P10 pull-up selection bit
Pull-up transistor P107/KI3 Pull-up transistor P106/KI2
0
Port P107 direction register
When the key input interrupt is selected, it is necessary to select the edge sense which uses falling edge.
1
0
Interrupt control register
INT2/Key input
interrupt request
1 Pull-up transistor P105/KI1 Pull-up transistor P104/KI0
___
Key input interrupt selection bit
Fig. 12 INT2 /Key input interrupt input circuit block diagram
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7
6
5
4 0
3
2
1
0 Port function control register
Address 6D16
Standby state selection bit 0: Pins P0 - P3 as external bus output 1: Pins P0 - P3 as port output Sub-clock output selection bit/Timer B2 clock source selection bit * Port-Xc selection bit = "0" (sub-clock not used) Timer B2 (event counter mode) clock source selection 0: TB2IN input 1: Main clock divided by 32 * Port-Xc selection bit = "1" (sub-clock used) Sub-clock output selection 0: Function as port P67 pin 1: Output sub-clock SUB from P67/TB2IN/ SUB pin Timer B1 internal connect selection bit 0: No internal connect 1: Internal connect to timer B2 Port P6 pull-up selection bit 0 0: With no pull-up transistor for pins P62/INT0, P63/INT1 1: With pull-up transistor for pins P62/INT0, P63/INT1 0: Always "0" Port P6 pull-up selection bit 1 * Key input interrupt selection bit = "0" 0: With no pull-up transistor for P64/INT2 pin 1: With pull-up transistor for P64/INT2 pin * Key input interrupt selection bit = "1" 0: With port function, no pull-up transistor for P64/INT2 pin 1: With key input interrupt, pull-up transistor for P64/INT2 pin Port P10 pull-up selection bit 0: With no pull-up transistor for pins P104 - P107 1: With pull-up transistor for pins P104 - P107 Key input interrupt selection bit 0: INT2 interrupt 1: Key input interrupt
Fig. 11 Bit configuration of port function control register
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TIMER
There are eight 16-bit timers. They are divided by type into timer A(5) and timer B(3). The timer I/O pins are also used as I/O pins for ports P5 and P6. To use these pins as timer input pins, the port direction register bit corresponding to the pin must be cleared to "0" to specify the input mode.
(1) Timer mode [00]
Figure 14 shows the bit configuration of the timer Ai mode register during timer mode. Bits 0, 1, and 5 of timer Ai mode register must always be "0" in the timer mode. Bit 3 is ignored if bit 4 is "0". Bits 6 and 7 are used to select the timer counter source. The counting of the selected clock starts when the count start flag is "1" and stops when it is "0". Figure 15 shows the bit configuration of the count start flag. The counter is decremented. An interrupt is caused and the interrupt request bit of the timer Ai interrupt control register is set when the contents becomes 000016. At the same time, the contents of the reload register are transferred to the counter, and count is continued.
TIMER A
Figure 13 shows a block diagram of timer A. Timer A has four modes; timer mode, event counter mode, one-shot pulse mode, and pulse width modulation mode. The mode is selected with bits 0 and 1 of the timer Ai mode register (i = 0 to 4). Each of these modes is described below.
Data bus (odd)
Data bus (even) (Low-order 8 bits) Clock source selection (High-order 8 bits)
f2 f16 f64 f512
* Timer * One-shot * Pulse width modulation Timer (gate function)
Reload register(16)
Counter(16) Up/Down
Always decremented except in event count mode
Address
Timer A0 4716 4616 Timer A1 4916 4816 Timer A2 4B16 4A16 Timer A3 4D16 4C16 Timer A4 4F16 4E16
TAi IN
(i = 0 - 4)
Polarity selection
Event counter
Count start flag (Address 4016)
External trigger
Down count Up-down flag (Address 4416)
Pulse output Toggle flip-flop TAi OUT
(i = 0 - 4)
Fig. 13 Block diagram of timer A
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When bit 2 of the timer Ai mode register is "1", the output is generated from TAiOUT pin. The output is toggled each time the contents of the counter reaches to 000016. When the contents of the count start flag is "0", "L" is output from TAiOUT pin. When bit 2 is "0", TAiOUT can be used as a normal port pin. When bit 4 is "0", TAiIN can be used as a normal port pin. When bit 4 is "1", counting is performed only while the input signal from the TAiIN pin is "H" or "L" as shown in Figure 16. Therefore, this can be used to measure the pulse width of the TAiIN input signal. Whether to count while the input signal is "H" or while it is "L" is determined by bit 3. When bit 3 is "1", counting is performed while the TAiIN pin input signal is "H" and when bit 3 is "0", counting is performed while it is "L".
Note that the duration of "H" or "L" on the TAiIN pin must be two or more cycles of the timer count sourse. When data is written to the timer Ai register with timer Ai halted, the same data is also written to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The counter is reloaded with new data from the reload register at the next reload time. The contents of the counter can be read at any time. When the value set in the timer Ai register is n, the timer frequency dividing ratio is 1/(n + 1).
Addresses Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register 5616 5716 5816 5916 5A16
7654321 0 0 00
0 0 : Always "00" in timer mode 0 : No pulse output (TAiOUT is normal port pin) 1 : Pulse output 0 ! : No gate function (TAiIN is normal port pin) 1 0 : Count only while TAiIN input is "L" 1 1 : Count only while TAiIN input is "H"
0 : Always "0" in timer mode Clock source selection bit 0 0 : Select f2 0 1 : Select f16 1 0 : Select f64 1 1 : Select f512
Fig. 14 Timer Ai mode register bit configuration during timer mode
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76543210
Count start flag (Stop at "0", Start at "1") Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag
Address 4016
Fig. 15 Count start flag bit configuration
Selected clock source fi
TAiN
Timer mode register Bit 4 1 Bit 3 0
Timer mode register Bit 4 1 Bit 3 1
Fig. 16 Count waveform when gate function is available
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(2) Event counter mode [01]
Figure 17 shows the bit configuration of the timer Ai mode register during the event counter mode. In the event counter mode, the bit 0 of the timer Ai mode register must be "1" and bits 1 and 5 must be "0". The input signal from the TAiIN pin is counted when the count start flag shown in Figure 15 is "1" and counting is stopped when it is "0". Count is performed at the fall of the input signal when bit 3 is "0" and at the rise of the signal when it is "1". In the event counter mode, whether to increment or decrement the count can be selected with the up-down flag or the input signal from the TAiOUT pin. When bit 4 of the timer Ai mode register is "0", the up-down flag is used to determine whether to increment or decrement the count (decrement when the flag is "0" and increment when it is "1"). Figure 18 shows the bit configuration of the up-down flag. When bit 4 of the timer Ai mode register is "1", the input signal from the TAiOUT pin is used to determine whether to increment or decrement the count. However, note that bit 2 must be "0" if bit 4 is "1". Because TAiOUT pin becomes an output pin with pulse output if bit 2 is "1". The count is decremented when the input signal from the TAiOUT pin is "L" and incremented when it is "H". Determine the level of the input signal from the TAiOUT pin before an effective edge is input to the TAiIN pin. An interrupt request signal is generated and the interrupt request bit of the timer Ai interrupt control register is set when the counter reaches 000016 (decrement count) or FFFF16 (increment count). At the same time, timers A0 and A1 transfer the contents of the reload register to the counter and continue counting. Timers A2, A3, and A4 transfer the contents of the reload register to the counter and continue count when bit 6 of the corresponding timer Ai mode register is "0", but when bit 6 is "1", they continue counting without transferring the contents of the reload register to the counter. When bit 2 is "1", the waveform of which polarity is reversed each time the counter reaches 000016 (decrement count) or FFFF16 (increment count) is output from TAiOUT pin. If bit 2 is "0", the TAiOUT pin can be used as a normal port pin. However, if bit 4 is "1" and the TAiOUT pin is used as an output pin, the output from the TAiOUT pin changes the count direction. Therefore, bit 4 must be "0" unless the output from the TAiOUT pin is used to select the count direction. Data write and data read are performed in the same way as for the timer mode. That is, when data is written to timer Ai which is halted, it is also written to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not the counter. The counter is reloaded with new data from the reload register at the next reload time and continues counting. For timers A2, A3, and A4, the contents of the reload register is not reloaded in the counter when bit 6 of the corresponding timer Ai mode register is "1". The contents of the counter can be read at any time.
Addresses Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register 5616 5716 5816 5916 5A16
76543210 0 01
0 1 : Always "01" in event counter mode 0 : No pulse output 1 : Pulse output 0 : Count at the falling edge of input signal 1 : Count at the rising edge of input signal 0 : Increment or decrement according to up-down flag 1 : Increment or decrement according to TAiOUT pin input signal level 0 : Always "0" in event counter mode This bit is available for times A2, A3, and A4. 0 : Reload 1 : No reload This bit is available for timer A3. 0 : Two-phase pulse signal processing in the same manner as timer A2 1 : Two-phase pulse signal processing in the same manner as timer A4
Fig. 17 Timer Ai mode register bit configuration during event counter mode
76543210
Up-down flag
Addresses 4416
Timer A0 up-down flag Timer A1 up-down flag Timer A2 up-down flag Timer A3 up-down flag Timer A4 up-down flag Timer A2 two-phase pulse signal processing selection bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Timer A3 two-phase pulse signal processing selection bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Timer A4 two-phase pulse signal processing selection bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode
Fig. 18 Up-down flag bit configuration
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Furthermore, in the event counter mode, whether to increment or decrement the counter can also be determined by supplying two kinds of pulses of which phases differ by 90 to timer A2, A3, or A4. There are two types of two-phase pulse signal processing operations. One uses timer A2 and the other uses timer A4. Timer A3 can select one of these two operations with bit 7 of the timer A3 mode register. In both processing operations, two kinds of pulses of which phases differ by 90 are input to the TAjOUT (j = 2 to 4) pin and TAjIN pin respectively. After the level of the TA2OUT pin changes from "L" to "H" with timer A2 used, as shown in Figure 19, the count is incremented when a rising edge is input to the TA2IN pin and the count is decremented when the falling edge is input. For timer A4, as shown in Figure 20, when a phase related pulse with a rising edge input to the TA4IN pin is input after the level of TA4OUT pin changes from "L" to "H", the count is incremented at the respective rising edge and falling edge of the TA4OUT pin and TA4IN pin. When a phase related pulse with a falling edge input to the TA4OUT pin is input after the level of TA4IN pin changes from "H" to "L", the count is decremented at the respective rising edge and falling edge of the TA4IN pin and TA4OUT pin. When performing this two-phase pulse signal processing, bits 0 and 4 of the timer Aj mode register must be set to "1" and bits 1, 2, 3, and 5 must be set to "0" as shown in Figure 21. Bit 7 is used to select whether to perform two-phase pulse signal processing for timer A3 in the same manner as timer A2 or as timer A4. When this bit is "0", two-phase pulse signal processing for timer A3 is performed in the same manner as timer A2 and when it is "1", it is performed in the same manner as timer A4. This bit is ignored for timers A2 and A4. Note that bits 5, 6, and 7 of the up-down flag (address 4416) are the two-phase pulse signal processing selection bits for timers A2, A3, and A4, respectively. Each timer operates in the normal event counter mode when the corresponding bit is "0" and performs two-phase pulse signal processing when it is "1". Count is started by setting the count start flag to "1". Data write and read are performed in the same way as for the normal event counter mode. Note that the port direction register of the input port must be set to the input mode because two-phase pulse signal is input. Also, there can be no pulse output in this mode.
TA2OUT
TA2IN
Increment Increment Increment Decrement Decrement Decrement count count count count count count
Fig. 19 Two-phase pulse signal processing operation of timer A2
TA4OUT
Increment count at each edge Decrement count at each edge
TA4IN
Increment count at each edge Decrement count at each edge
Fig. 20 Two-phase pulse signal processing operation of timer A4
Addresses Timer A2 mode register 5816 5916 5A16
76543210 010001
Timer A3 mode register Timer A4 mode register
0 1 : Always "01" in event counter mode 0 1 0 0 : Always "0100" when processing two-phase pulse signal 0 : Reload 1 : No reload This bit is avilable for timer A3 0 : Two-phase pulse signal processing in the same manner as timer A2 1 : Two-phase pulse signal processing in the same manner as timer A4
Fig. 21 Timer Aj mode register bit configuration when performing two-phase pulse signal processing in event counter mode
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NA
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) One-shot pulse mode [10]
Figure 22 shows the bit configuration of the timer Ai mode resister during the one-shot pulse mode. In the one-shot pulse mode, bit 0 and bit 5 must be "0" and bit 1 and bit 2 must be "1". The trigger is enabled when the count start flag is "1". The trigger can be generated by software, or it can be input from the TAiIN pin. Software trigger is selected when bit 4 is "0", and the input signal from the TAiIN pin is used as the trigger when bit 4 is "1". Bit 3 is used to determine whether to trigger at the fall of the trigger signal or at the rise. The trigger is at the fall of the trigger signal when bit 3 is "0" and at the rise of the trigger signal when bit 3 is "1". Software trigger is generated by setting the bit of the one-shot start flag corresponding to each timer. Figure 23 shows the bit configuration of the one-shot start flag. As shown in Figure 24, when a trigger signal is received, the counter counts the clock selected by bits 6 and 7. If the contents of the counter is not 000016, the TAiOUT pin goes "H" when a trigger signal is received. The count direction is decrement. When the counter reaches 000116, the TAiOUT pin goes "L" and count is stopped. The contents of the reload register is transferred to the counter. At the same time, an interrupt request signal is generated, and the interrupt request bit of the timer Ai interrupt control register is set. This is repeated each time a trigger signal is received. The output pulse width is 1 pulse frequency of the selected clock ! (counter's value at the time of trigger). If the count start flag is "0", the level of the TAiOUT pin goes "L". Therefore, the counter's value corresponding to the desired pulse width must be written to timer Ai before setting "1" to the timer Ai count start flag. As shown in Figure 25, a trigger signal can be received before the operation for the previous trigger signal is completed. In this case, the contents of the reload register is transferred to the counter by the trigger, and then that value is decremented. Except when retriggering while operating, the contents of the reload register is not transferred to the counter by triggering. When retriggering, there must be at least two timer count source cycles before a new trigger can be issued.
Addresses Timer A0 mode register Timer A1 mode register Timer A2 mode register 5616 5716 5816 5916 5A16
76543210 0 110
Timer A3 mode register Timer A4 mode register
1 0 : Always "10" in one-shot pulse mode 1 : Always "1" in one-shot pulse mode 0 ! : Software trigger 1 0 : Trigger at the falling edge of TAiIN input 1 1 : Trigger at the rising edge of TAiIN input 0 : Always "0" in one-shot pulse mode Clock source selection 0 0 : Select f2 0 1 : Select f16 1 0 : Select f64 1 1 : Select f512
Fig. 22 Timer Ai mode register bit configuration during one-shot pulse mode
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Data write is performed in the same way as for the timer mode. When data is written in timer Ai halted, it is also written to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The counter is reloaded with new data from the reload register at the next reload time and continues counting. Undefined data is read when timer Ai is read.
76543210 One-shot start flag
Address 4216
Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag Fig. 23 One-shot start flag bit configuration
Selected clock source fi TAiIN (rising edge is selected)
TAiOUT In this case, the contents of the reload register is 000316.
Fig. 24 Pulse output example when external rising edge is selected
Selected clock source fi TAiIN (rising edge is selected)
TAiOUT In this case, the contents of the reload register is 000416.
Fig. 25 Example when trigger is re-issued during pulse output
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Pulse width modulation mode [11]
Figure 26 shows the bit configuration of the timer Ai mode register during the pulse width modulation mode. In the pulse width modulation mode, bits 0, 1, and 2 must be set to "1". Bit 5 is used to determine whether to perform as the 16-bit length pulse width modulator or the 8-bit length pulse width modulator. 16bit length pulse width modulator is selected when bit 5 is "0" and 8-bit length pulse width modulator is selected when bit 5 is "1". The 16-bit length pulse width modulator is described first. The pulse width modulator can be started with a software trigger or with an input signal from a TAiIN pin (external trigger). The software trigger mode is selected when bit 4 is "0". Pulse width modulator is started and pulse is output from the TAiOUT pin when the timer Ai start flag is set to "1". The external trigger mode is selected when bit 4 is "1". Pulse width modulator starts when a trigger signal is input from the TAiIN pin when the timer Ai start flag is "1". Whether to trigger at the fall or rise of the trigger signal is determined by bit 3. The trigger is at the fall of the trigger signal when bit 3 is "0" and at the rise when it is "1". When data is written to timer Ai with the pulse width modulator halted, it is written to the reload register and the counter. Then when the timer Ai start flag is set to "1" and a software trigger or an external trigger is issued to start modulation, the waveform shown in Figure 27 is output continuously. Once modulation is started, triggers are not accepted. When the value in the reload register is m, the duration "H" of pulse is 1 !m selected clock frequency and the output pulse period is 1 ! (2 16 - 1). selected clock frequency An interrupt request signal is generated and the interrupt request bit of the timer Ai interrupt control register is set at each fall of the output pulse. The width of the output pulse is changed by updating timer data. The update can be performed at any time. The output pulse width is changed at the rise of the pulse after data is written to the timer. The contents of the reload register is transferred to the counter just before the rise of the next output pulse so that the pulse width is changed from the next output pulse. Undefined data is read when timer Ai is read. The 8-bit length pulse width modulator is described next. The 8-bit length pulse width modulator is selected when bit 5 of the timer Ai mode register is "1".
The reload register and the counter are both divided into 8-bit halves. The low-order 8 bits function as a prescaler and the high-order 8 bits function as the 8-bit length pulse width modulator. The prescaler counts the clock selected by bits 6 and 7. A pulse is generated when the counter reaches 000016 as shown in Figure 28. At the same time, the contents of the reload register is transferred to the counter, and count is continued.
Addresses Timer A0 mode register Timer A1 mode register Timer A2 mode register 5616 5716 5816 5916 5A16
76 543210 111
Timer A3 mode register Timer A4 mode register
1 1 : Always "11" in pulse width modulation mode 1 : Always "1" in pulse width modulation mode 0 ! : Software trigger 1 0 : Trigger at the falling of TAiIN input 1 1 : Trigger at the rising of TAiIN input 0 : 16 bit pulse width modulator 1 : 8 bit pulse width modulator
Clock source selection bit 0 0 : Select f2 0 1 : Select f16 1 0 : Select f64 1 1 : Select f512 Fig. 26 Timer Ai mode register bit configuration during pulse width modulation mode
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Therefore, if the low-order 8 bits of the reload register is n, the period of the generated pulse is 1 ! (n + 1). selected clock frequency The high-order 8 bits function as an 8-bit length pulse width modulator using this pulse as input. Its operation is the same as for 16-bit length pulse width modulator except it has a length of 8 bits. When the highorder 8 bits' contents of the reload register is m, the duration "H" of pulse is
1 ! (n + 1) ! m. selected clock frequency And the output pulse period is 1 ! (n + 1) ! (28 - 1). selected clock frequency
1 / fi ! (216 - 1)
Selected clock source fi
TAiIN (rising edge is selected)
This trigger is not accepted 1 / fi ! (m)
TAiOUT In this case, the contents of the reload register is 000316. Fig. 27 16-bit length pulse width modulator output pulse example
1 / fi ! (n + 1) ! (28 - 1)
Selected clock source fi
TAiIN (falling edge is selected) 1 / fi ! (n + 1) Prescaler output (when n = 2) 1 / fi ! (n + 1) ! (m)
8-bit length pulse width modulator output (when m = 2) Fig. 28 8-bit length pulse width modulator output pulse example
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TIMER B
Figure 29 shows a block diagram of timer B. Timer B has three modes; timer mode, event counter mode, and pulse period measurement/pulse width measurement mode. The mode is selected with bits 0 and 1 of the timer Bi mode register (i = 0 to 2). Timer B2 can also be used as the clock timer of which clock source is the main clock or the sub-clock divided by 32. Additionally, timer B2 can be internally connected to timer B1 (cascade connection). Each of these modes is described below.
(1) Timer mode [00]
Figure 30 shows the bit configuration of the timer Bi mode register during the timer mode. Bits 0 and 1 of the timer Bi mode register must always be "0" in the timer mode. Bits 6 and 7 are used to select the clock source. The counting of the selected clock starts when the count start flag is "1" and stops when it is "0".
As shown in Figure 15, the timer Bi count start flag is at the same address as the timer Ai count start flag. The count is decremented. When the contents of the counter becomes 000016, an interrupt request occurs and the interrupt request bit of the timer Bi interrupt control register is set. At the same time, the contents of the reload register is stored in the counter, and count is continued. Timer Bi does not have a pulse output function or a gate function like timer A. When data is written to timer Bi halted, it is written to the reload register and the counter. When data is written to timer Bi which is busy, the data is written to the reload register, but not to the counter. The counter is reloaded with new data from the reload register at the next reload time and continues counting. The contents of the counter can be read at any time.
Data bus (odd)
Clock source selection f2 f16 f64 f512 * Timer * Pulse period measurement/pulse width measurement Polarity selection and edge pulse generator
Data bus (even) (Low-order 8 bits) (High-order 8 bits)
Reload register (16)
TBi IN (i = 0 - 2)
Event counter
Counter (16)
fC32 (Note 1) TB2 overflow signal (Note 2)
Count start flag (Address 4016)
Addresses Timer B0 5116 5016 Timer B1 5316 5216 Timer B2 5516 5416
Counter reset circuit
Notes 1. Clock source of clock timer; Only timer B2 can select it (refer to Fig. 65) 2. Only timer B1 can select it (internal connect mode) Fig. 29 Timer B block diagram
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode [01]
Figure 31 shows the bit configuration of the timer Bi mode register during the event counter mode. In the event counter mode, the bit 0 of the timer Bi mode register must be "1" and bit 1 must be "0". The input signal from the TBiIN pin is counted when the count start flag is "1", and counting is stopped when it is "0". Counting is performed at the fall of the input signal when bits 2 and 3 are "0" and at the rise of the input signal when bit 3 is "0" and bit 2 is "1". When bit 3 is "1" and bit 2 is "0", counting is performed at the rise and fall of the input signal. When the sub-clock (32 kHz) oscillation circuit is used and others, and the event counter mode is selected, timer B2 functions as the clock timer and the original functions as timer B2 in the event counter mode are lost. For details, refer to "(4) Clock timer". When the internal connect mode which connects timer B1 to timer B2 is selected, the original function as timer B1 in the event counter mode is lost. For details, refer to "(5) Internal connect mode". Data write, data read, and interrupt generation are performed in the same way as for the timer mode.
When bit 3 is "1", the pulse width measurement mode is selected. The pulse width measurement mode is similar to the pulse period measurement mode except that the clock is counted from the fall of the TBiIN pin input signal to the next rise or from the rise of the input signal to the next fall as shown in Figure 34.
Addresses Timer B0 mode register 5B16 5C16 5D16
76543210
Timer B1 mode register Timer B2 mode register
!0!!0 0
0 0 : Always "00" in timer mode ! ! : Not used in timer mode and may be any 0 : Always "0" in timer mode (timer B0) ! :Not used in timer mode (timers B1, B2) ! :Not used in timer mode Clock source selection bit 0 0 : Select f2 0 1 : Select f16 1 0 : Select f64 1 1 : Select f512
(3) Pulse period measurement/pulse width measurement mode [10]
Figure 32 shows the bit configuration of the timer Bi mode register during the pulse period measurement/pulse width measurement mode. In the pulse period measurement/pulse width measurement mode, bit 0 must be "0" and bit 1 must be "1". Bits 6 and 7 are used to select the clock source. The selected clock is counted when the count start flag is "1", and counting stops when it is "0". The pulse period measurement mode is selected when bit 3 is "0". In the pulse period measurement mode, the selected clock is counted during the interval starting at the fall of the input signal from the TBiIN pin to the next fall or at the rise of the input signal to the next rise. And then, the result is stored in the reload register. In this case, the reload register acts as a buffer register. When bit 2 is "0", the clock is counted from the fall of the input signal to the next fall. When bit 2 is "1", the clock is counted from the rise of the input signal to the next rise. In the case of counting from the fall of the input signal to the next fall, counting is performed as follows. As shown in Figure 33, when the fall of the input signal from TBiIN pin is detected, the contents of the counter is transferred to the reload register. Next the counter is cleared and count is started from the next clock. When the fall of the next input signal is detected, the contents of the counter is transferred to the reload register once more, the counter is cleared, and counting is started. The period from the fall of the input signal to the next fall is measured in this way. After the contents of the counter is transferred to the reload register, an interrupt request signal is generated and the interrupt request bit of the timer Bi interrupt control register is set. However, no interrupt request signal is generated when the contents of the counter is transferred first time to the reload register after the count start flag is set to "1".
Fig. 30 Timer Bi mode register bit configuration during timer mode
Addresses Timer B0 mode register 5B16 5C16 5D16
76543210
Timer B1 mode register Timer B2 mode register
!!! 0
01
0 1 : Always "01" in event counter mode 0 0 : Count at the falling edge of input signal 0 1 : Count at the rising edge of input signal 1 0 : Count at the both falling edge and rising edge of input signal 0 : Always "0" in event counter mode (timer B0) ! : Not used in event counter mode (timers B1, B2) ! ! ! : Not used in event counter mode
Fig. 31 Timer Bi mode register bit configuration during event counter mode
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When timer Bi is read, the contents of the reload register is read. Note that, in this mode, the interval from the fall of the TBiIN pin input signal to the next rise or from the rise to the next fall must be at least two cycles of the timer count source. Timer Bi overflow flag which is bit 5 of the timer Bi mode register is set to "1" when the timer Bi counter reaches 000016. This flag is cleared by writing to the corresponding timer Bi mode register. By reading this flag, the reason why the interrupt request signal is generated, which is the completion of measurement or the counter overflow, can be detected. An interrupt request signal may occur because the counter value is particularly undefined just after counting starts. Accordingly, make sure to detect the occurrence reason of an interrupt request signal with the timer Bi overflow flag. This flag is "1" at reset. When using timer B2 as the clock timer and using timer B1 in the internal connect mode, functions in this mode are lost.
7
65
43 0
21 1
0 0
Addresses Timer B0 mode register 5B16 Timer B1 mode register 5C16 Timer B2 mode register 5D16 1 0 : Always "10" in pulse period measurement/pulse width measurement mode 0 0 : Count from the falling edge of input signal to the next falling one 0 1 : Count from the rising edge of input signal to the next rising one 1 0 : Count from the falling edge of input signal to the next rising one and from the rising edge to the next falling one 0 : Always "0" in pulse period measurement/pulse width measurement mode (timer B0) ! : Not used in pulse period measurement/pulse width measurement mode (timers B1, B2) Timer Bi overflow flag Clock source selection bit 0 0 : Select f2 0 1 : Select f16 1 0 : Select f64 1 1 : Select f512
Fig. 32 Timer Bi mode register bit configuration during pulse period measurement/pulse width measurement mode
Selected clock source fi
TBiIN
Reload registerCounter
Counter0
Count start flag
Interrupt request signal
Fig. 33 Pulse period measurement mode operation (example of measuring the interval from the falling edge to next falling one)
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selected clock source fi
TBiIN
Reload registerCounter
Counter0
Count start flag
Interrupt request signal Fig. 34 Pulse width measurement mode operation
(4) Clock timer
When the port-XC selection bit of the oscillation circuit control register 0 (refer to Figure 63) is set to "1" to make the sub-clock oscillation circuit active, timer B2 can function as the clock timer, which uses clock fC32 as the clock source. Clock fC32 is the sub clock (32 kHz) divided by 32. Additionally, when the port-Xc selection bit is set to "0" not to use the sub-clock and the timer B2 clock source selection bit of the port function control register (refer to Figure 11) is set to "1", timer B2 can functions as the clock timer, which uses clock fc32 as the clock source. Clock fc32 is the main clock divided by 32. Figure 35 shows the timer B2 mode register bit configuration when timer B2 is used as the clock timer. As shown in Figure 35, the event counter mode must be selected for timer B2. For how to use the clock timer, refer to the section on clock generating circuit. 01 234 567 !!! !0 1 0 1 Address Timer B1 mode register 5C16 Timer B2 mode register 5D16 0 1 : Always "01" in event counter mode 0 1 : Count at the rising edge of input signal !!!!: Not used in event counter mode Fig. 35 Timer B1 mode register bit configuration when timer B1 is used in the internal connect mode and timer B2 mode register bit configuration when timer B2 is used as clock timer
(5) Internal connect mode
When the timer B1 internal connect selection bit of the port function control register (refer to Figure 11) is set to "1", timer B1 uses the timer B2's overflow signal as the clock source and timer B1 is internally connected to timer B2 (cascade connection). The internal connect mode makes timers B1 and B2 function as 16 + 16 bit-timer with the timer B2's clock source. Figure 35 shows the timer B1 mode register bit configuration when using timer B1 in the internal connect mode. Set timer B1 in the event counter mode as shown in Figure 35.
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SERIAL I/O PORTS
Three independent serial I/O ports are provided. Figure 36 shows a block diagram of the serial I/O ports. Table 5 shows the functional differences of three serial I/O ports (UART 0, 1, 2).
Bits 0, 1, and 2 of the UARTi (i = 0, 1, 2) transmit/receive mode register shown in Figure 37 are used to determine whether to use port P8 or port P10 as a parallel port, a clock synchronous serial I/O port, or an asynchronous serial I/O port (UART) using start and stop bits.
Data bus (odd) Data bus (even) Bit converter 0 00 0 00 (Note)
Receive 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 buffer register
UART0 (Addresses 3716, 3616) UART1 (Addresses 3F16, 3E16) UART2 (Addresses 6B16, 6A16)
RxDi
Bit rate generator UART0 (Address 3116) UART1 (Address 3916) UART2 (Address 6516) Internal 1/(n + 1) Divider
Receive register 1/16 Divider UART receive
Receive control circuit
Receive clock
Clock synchronous 1/16 Divider UART transmission
Clock source selection f2 f 16 f 64 f 512
External
Clock synchronous 1/2 Divider
Clock synchronous (Internal clock)
Transmission control circuit
Transmission clock
TxDi
Transmisson register Transmission D8 D7 D6 D5 D4 D3 D2 D1 D0 buffer register
UART0 (Addresses 3316, 3216) UART1 (Addresses 3B16, 3A16) UART2 (Addresses 6716, 6616)
Clock synchronous (Internal clock)
Clock synchronous (External clock)
CLKi
Polarity reversing circuit
CTSi/RTSi (Note)
(Note)
Bit converter Data bus (odd)
(Note)
Note. UART2 does not include the bit converter, the polarity reversing circuit and the RTSi output. Fig. 36 Serial I/O port block diagram
Data bus (even)
76543210
Addresses UART 0 transmit/receive mode register 3016 UART 1 transmit/receive mode register 3816 Serial I/O mode selection bits 0 0 0 : Parallel port 0 0 1 : Clock synchronous 1 0 0 : 7-bit UART 1 0 1 : 8-bit UART 1 1 0 : 9-bit UART Internal clock/External clock selection bit 0 : Internal clock 1 : External clock Stop bit length selection bit 0 : 1 stop bit 1 : 2 stop bits Odd/even parity selection bit 0 : Odd parity 1 : Even parity Parity enable bit 0 : No parity 1 : With parity Sleep function selection bit 0 : No sleep 1 : Sleep
76543210
Address UART 2 transmit/receive mode register 6416 Serial I/O mode selection bits (Note) 0 0 0 : Parallel port 0 0 1 : Clock synchronous 1 0 0 : 7-bit UART 1 0 1 : 8-bit UART 1 1 0 : 9-bit UART Internal clock/External clock selection bit 0 : Internal clock 1 : External clock Stop bit length selection bit 0 : 1 stop bit 1 : 2 stop bits Odd/even parity selection bit 0 : Odd parity 1 : Even parity Parity enable bit 0 : No parity 1 : With parity
Note. The switch of A-D conversion interrupt and UART2 transmit/receive interrupt is performed by bits 0 to 2. When selecting a parallel port, A-D conversion interrupt is valid. When selecting a clock synchronous serial I/O port or a UART, UART2 transmit/receive interrupt is valid.
Fig. 37 UARTi transmit/receive mode register bit configuration
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The interrupt vector and the interrupt control register are common to the A-D conversion interrupt and UART2 transmit/receive interrupt. It is switched by a selection of UART2 function as shown in Figure 37 and Table 5. Figure 38 shows the connections of receiver/transmitter.
Figures 39 and 40 show the bit configuration of the UARTi transmit/ receive control register. Each communication method is described below.
Receiver block diagram
Data bus (odd) Data bus (even)
Bit converter 0 0 0 0 0 0
7 bit 8 bit 9 bit No Parity
(Note) D2 D1 D0
Receive buffer register
0
D8
9 bit
D7
D6
D5
D4
D3
RxDi
2 stop bit Stop bit Stop bit 1 stop bit
Parity Parity bit
8 bit 9 bit Synchronous Receive register
7 bit 8 bit 7 bit Synchronous
Synchronous
Transmitter block diagram
Data bus (odd) Data bus (even)
Bit converter D8
2 stop bit Stop bit Stop bit Parity 7 bit 8 bit 9 bit Parity bit No Parity 8 bit 1 stop bit "0" Synchronous 7 bit
(Note) D2 D1 D0
Transmission buffer register
D7
D6
D5
D4
D3
7 bit 8 bit 9 bit 9 bit Synchro- Synchronous nous
TxDi
"0"
Transmission register
Note. UART2 does not include the bit converter.
Fig. 38 Receiver and transmitter block diagram Table 5. Differences between UART0, UART1 and UART2
___
Communication method UART0 Selection of clock synchronous or asynchronous (UART) Selection of clock synchronous or asynchronous (UART) Selection of clock synchronous or asynchronous (UART)
CTS ___
input/ RTS output
___
Interrupt Transmit and receive (2 systems) Transmit and receive (2 systems) Transmit/receive (1 system) (Note)
Both___ input CTS and RTS output
___
Selection of data output, CLK polarity, Multiple clocks Sleep function output transfer format Available Available Available
UART1
Both___ input CTS and RTS output
___
Available
Nothing
Available
UART2
Only CTS input
Nothing
Nothing
Nothing
Note. The interrupt vector and the interrupt control register are common to the A-D conversion interrupt and UART2 transmit/receive interrupt. It is switched by a selection of UART2 function.
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I LIM E
NA
RY
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5 TxS
4
3
2
1
0
Addresses UART0 transmit/receive control register 0 3416 UART1 transmit/receive control register 0 3C16 BRG count source selection bits 00 : Select f2 01 : Select f16 10 : Select f64 11 : Select f512
CTS/RTS selection bit 0 : Select CTS 1 : Select RTS
TFM CPL
Tx R/C EPTY
CS1 CS0
Transmission register empty bit
CTS, RTS enable bit 0 : Enble CTS and RTS 1 : Disable CTS and RTS (I/O port)
Data output selection bit 0 : CMOS output 1 : N-channel open-drain output CLK polarity selection bit 0 : In transferring, transmit data is output at the CLKi's falling edge or received data is input at the CLKi's rising edge. Not in transferring, CLKi level is "H". 1 : In transferring, transmit data is output at the CLKi's rising edge or received data is input at the CLKi's falling edge. Not in transferring, CLKi level is "L". Transfer format selection bit 0 : LSB first 1 : MSB first
7
6
5
4
3 RI
2 RE
1 TI
0 TE
Addresses UART0 transmit/receive control register 1 3516 UART1 transmit/receive control register 1 3D16 Transmit enable flag Transmit buffer empty flag Receive enable bit Receive completing flag Overrun error flag Framing error flag Parity error flag Error sum flag
SUM PER FER OER
Fig. 39 UART0, UART1 transmit/receive control registers bit configuration
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I LIM E
NA
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0
Addresses UART2 transmit/receive control register 0 6816
Tx R/C EPTY
CS1 CS0
BRG count source selection bits 00 : Select f2 01 : Select f16 10 : Select f64 11 : Select f512
CTS enable bit 0 : Enable CTS 1 : Disable CTS (I/O port)
Transmission register empty bit
7
6
5
4
3 RI
2 RE
1 TI
0 TE
Addresses UART2 transmit/receive control register 1 6916
SUM PER FER OER
Transmit enable flag Transmit buffer empty flag Receive enable bit Receive completing flag Overrun error flag Framing error flag Parity error flag Error sum flag
Fig. 40 UART2 transmit/receive control register bit configuration
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NA
RY
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CLOCK SYNCHRONOUS SERIAL COMMUNICATION
A case where communication is performed between two clock synchronous serial I/O ports as shown in Figure 41 will be described. (The transmission side will be denoted by subscript j and the receiving side will be denoted by subscript k.) Bit 0 of the UARTj transmit/receive mode register and UARTk transmit/ receive mode register must be set to "1", and bits 1 and 2 must be "0". The length of the transmission data is 8 bits. Bit 3 of the UARTj transmit/receive mode register of the clock sending side is cleared to "0" to select the internal clock. Bit 3 of the UARTk transmit/receive mode register of the clock receiving side is set to "1" to select the external clock. Bits 4, 5 and 6 are ignored in the clock synchronous mode. Bit 7 must always be "0". The clock source is selected by bit 0 (CS0) and bit 1 (CS1) of the clock sending side UARTj transmit/receive control register 0. When the contents of the bit rate genarator is n, as shown in Figure 36, the selected clock is divided by (n + 1), then by 2, passed through a transmission control circuit, and output as transmission clock CLKj. Therefore, when the selected clock is fi, Bit Rate = fi / {(n + 1) ! 2} On the clock receiving side, the CS0 and CS1 bits are ignored because an external clock is selected.
The bit 2 of the clock sending side___ UARTj transmit/receive control register 0 is cleared to "0" to select CTSj input. The bit 2 of the clock ___ receiving side is set to "1" to select RTSk output. ___ ___ Whether to use signals CTS and RTS is determined by bit 4 of___ the UART transmit/receive control register 0. Set bit 4 to "0" when CTS ___ and RTS signals ___used, and to "1" when they are not used. ___ are UART2 has the CTS input function, but that does not have the RTS output function___ to ___ 40.) (refer Figure ___ ___ When signals CTS and RTS are not used, the CTS/RTS pin can be used as a normal port. The following describes the case when signals ___ ___ ___ ___ CTS and RTS are used. When signals CTS and RTS are not used, the ___ ___ CTSj input condition is unnecessary and there is no RTSk output. Output driver format of the transmit data output pin (TXDj), which is the CMOS output or the N-channel open-drain output, is selected with bit 5 (TXS) of the UARTj transmit/receive control register 0. When bit 5 is "0", the CMOS output format is selected. When bit 5 is "1", the N-channel open-drain output format is selected. When the N-channel open-drain output format is selected, make sure to pull-up the data line using a pull-up resistor.
TxDj UARTj transmission register
TxDk UARTk transmission register
UARTj transmission buffer register
UARTk transmission buffer register
UARTj receive buffer register RxDj UARTj receive register UARTj transmit/receive mode register RxDk
UARTk receive buffer register
UARTk receive register UARTk transmit/receive mode register
0
!
!
!
0
0
0
1 CLKj CLKk
0
!
!
!
1
0
0
1
UARTj transmit/receive control register 0 TFM CPL TxS
UARTk transmit/receive control register 0 TFM CPL TxS
CTSj RTSk
0
Tx EPTY
0
CS1 CS0
0
Tx EPTY
1
!
!
UARTj transmit/receive control register 1 SUM PER FER OER RI RE TI TE
UARTk transmit/receive control register 1 SUM PER FER OER RI RE TI TE
___
Note. UART2 does not include RTS output. The UART2 transmit/receive control register 0's bit configuration is partialy different. Fig. 41 Clock synchronous serial communication
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I LIM E
NA
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The internal/external clock polarity is selected with bit 6 (CPL) of the UARTj transmit/receive control register 0. When bit 6 is "0", transmit data is output at the CLKj's falling edge in transmitting, received data is input at the CLKk's rising edge in receiving, and the CLKi level is "H" not in transferring (transmitting/receiving). When bit 6 is "1", reversely, transmit data is output at the CLKj's rising edge in transmitting, received data is input at the CLKk's falling edge in receiving, and the CLKi level is "L" not in transferring. Bit transfer order of transmit/received data, which is LSB first or MSB first (Note), is selected with bit 7 (TFM) of the UARTj transmit/receive control register 0. LSB first is selected when bit 7 is "0", and MSB first is selected when bit 7 is "1". However, UART2's function is fixed to the function specified by TxS=CPL=TFM="0", and it cannot be changed. Note that, only in the UART0 transmission mode, the transmission clock can be output not only from the CLK0 pin but also from the other output pins (CLKS0, CLKS1). Transmission clock output multipleselection mode is set with the serial transmit control register and others. For details, refer to the section on transmission. Note. When LSB first is selected, data is transmitted/received beginning at the least significant bit (LSB). When MSB first is selected, data is transmitted/received beginning at the most significant bit (MSB).
Transmission
Transmission is started when the bit 0 (TEj flag) of the UARTj transmit/ receive control register 1 is "1", bit 1 (TIj flag) of one is "0", and the ___ CTSj input is "L". Transmit data is output each time when the transmission clock (CLKj) level changes from "H" to "L" with bit 6 (CPL) of the UARTj transmit/ receive control register 0 "0" or is output each time when the CLKj level changes from "L" to "H" with CPL "1". For details, refer to Figure 42. In addition, transmit data is output beginning at the least significant bit (LSB) with bit 7 (TFM) of the UARTj transmit/receive control register "0" or is output beginning at the most significant bit (MSB) with TFM "1". The TIj flag indicates whether the transmission buffer register is empty or not. It is cleared to "0" when date is written in the transmission buffer register and set to "1" when the contents of the transmission buffer register is transferred to the transmission register.
1 / fi ! ( n + 1 ) ! 2
Transmission clock TEj
TIj
Write in transmission buffter register CTSj Transmission register Transmission buffter register
1 / fi ! ( n + 1 ) ! 2
CLKj (CPL = "0" ) (CPL = "1" ) TENDj
Stopped because TEj = "0"
TXDj
(TFM = "0" ) (TFM = "1" )
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
TXEPTYj
Fig. 42 Clock synchronous serial I/O timing
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IM REL
IN
Y AR
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When the transmission register becomes empty after its contents has been transmitted, data is automatically transferred from the transmission buffer register to the transmission register if the next transmission start condition is satisfied. When bit 2 of the UARTj ___ transmit/receive control register 0 is "1", CTSj input is ignored and transmission start is controlled only by the TEj flag and TIj flag. Once ___ transmission has started, the TEj flag, TIj flag, and CTSj signals are ignored until data transmission completes. Therefore, transmission ___ is not interrupt even when CTSj input is changed to "H" during transmission. ___ As shown in Figure 42, CTSj and flags TEj and TIj, which indicate the transmission start condition, are checked while the TENDj signal is "H". Therefore, data can be transmitted continuously when the next transmission data is written in the transmission buffer register and the TIj flag is cleared to "0" before the TENDj signal level becomes H". The bit 3 (TXEPTYj flag) of the UARTj transmit/receive control register 0 changes to "1" at the next cycle after the TENDj signal level becomes "H". Furthermore, the TxEPTYj flag changes to "0" when transmission starts. Therefore, this flag can be used to determine whether data transmission has been completed. When the TIj flag changes from "0" to "1", the interrupt request bit in the UARTj transmission (transmit/receive in UART2) interrupt control register is set to "1". Since UART0 has three output pins (CLK0, CLKS0, and CLKS1) for the transmission clock, the user can select one from these pins when using the internal clock. Accordingly, data can be transmitted to three external receive devices which will not receive data at the same time. Figure 43 shows the extrnal connection diagram example. To select the transmission clock output multiple-selection mode, it is necessary to set bits 5 and 4 of the serial transmit control register. In ___ addition, it is necessary to select the internal clock, to disable CTS ___ and RTS, and disable reception, with the UART0 transmit/receive mode register and the UART0 transmit/receive control register 0/1. Figure 44 shows the bit configuration of the serial transmit control register and Figure 45 shows the bit configuration of the UART0
transmit/receive mode register and the UART0 transmit/receive control register 0/1 in the transmission clock output multiple-selection mode. Furthermore, Table 6 shows the function of bits 5 and 4 (Transmission clock output pin selection bits, TC1 and TC0) of the serial transmit control register. As shown in Table 5, the transmission clock is output from the CLK0, CLKS0, or CLKS1 pin depending on TC1, TC0. Do not change the value of TC1 and TC0 during transferring. The transmission clock polarity also depends on bit 6 (CPL) of the UART0 transmit/receive control register 0. 7 6 5 4 3 2 1 0 Serial transmit control register Adress 6E16
TC1 TC0
Transmission clock output pin selection bits 0 0 : Normal mode (Clock is output only from CLK0) 0 1 : Multiple clocks are specified (Clock is output from CLK0) 1 0 : Multiple clocks are specified (Clock is output from CLKS0) 1 1 : Multiple clocks are specified (Clock is output from CLKS1)
Fig. 44 Bit configuration of serial transmit control register Table 6. Relationship between transmission clock output pin selection bits and pin functions Transmission clock P81 P82 P80 ___ ___ output pin selection bits RXD0 CTS0/RTS0 TC1 TC0 CLK0 CLKS0 CLKS1 ___ ___ 0 0 CLK0 RXD0 P8/CTS0/RTS0 0 1 CLK0 "H" (Note2) P80 1 0 "H" CLKS0 P80 1 1 "H" "H" (Note2) CLKS1 Notes 1. In this table, the CLK polarity selection bit (CPL) is "0". When CPL is "1", "H" in this table becomes "L". The polarity of CLK0, CLKS0, or CLKS1 also depends on CPL. 2. When bit 2 of the port P8 direction register is "1", "H" is output. When this bit is "0", floating is entered.
TXD0 UART 0 CLKS1 CLKS0 CLK0
DIN CLK
DIN CLK
DIN CLK
Note. Clock synchronous serial I/O communication and internal clock are used. This connection is applied only in transmission mode.
Fig. 43 External connection diagram example in the transmission clock output multiple-selection mode
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7 0
6
5
4
3 0
2 0
1 0
0 1 UART0 transmit/receive mode register
!!!
Address 3016
Receive
Receive starts when the bit 2 (REk flag) of the UARTk transmit/receive control register 1 is set to "1". ___ The RTSk output level is "H" when the REk flag is "0", but it ___ when is "L" the REk flag is "1" and the TIk flag is "0". Furthermore, the RTSk output level is "H" again when receiving restarts. The TIk flag is cleared to "0" by writing dummy data into the transmission buffer register. When ___ the RTSk output level is "L", receiving for the receive register is enabled. ___ UART2 does not have the RTS output function. When bit 6 (CPL) of the UARTk transmit/receive control register 0 is "0", the contents of the receive register is shifted by 1 bit each time when the receive clock (CLKk) changes from "L" to "H". When CPL is "1", the contents is shifted by 1 bit each time when CLKk changes from "H" to "L". These shifts are performed simultaneously with the data reception from the RXDk pin. When an 8-bit data is received, the contents of the receive register is transferred to the receive buffer register and the bit 3 (RIk flag) of the UARTk transmit/receive control register 1 is set to "1". In other words, the setting of the RIk flag to "1" indicates that the receive buffer register contains the received data. ___ When the TIk flag goes "0", RTSk output level goes "L" to indicate that the next data can be received. When the RIk flag changes from "0" to "1", the interrupt request bit of the UARTk receive (transmit/receive in UART2) interrupt control register is set to "1". Bit 4 (OERk flag) of the UARTk transmit/receive control register is set to "1" when the next data is transferred from the receive register to the receive buffer register while RIk flag is "1", and the OERk flag indicates that the next data was transferred to the receive buffer register before the contents of the receive buffer register was read. The RIk flag is cleared to "0" when reading the low-order byte to the receive buffer, when writing "0" to the REk flag, or when setting to be a parallel port. The OERk flag is cleared to "0" when writing "0" to the REk flag or when setting to be a parallel port. The FERk, PERk, and SUMk flags are ineffective in the clock synchronous communication. The received data in the receive buffer register is read into the data bus according to the LSB first (beginning at the least significant bit) when bit 7 (TEM) of the UARTk transmit/receive control register 0 is "0" or according to the MSB first (beginning at the most significant bit) when bit 7 is "1". As shown in Figure 36, with clock synchronous serial communication, data cannot be received unless the transmitter is operating because the receive clock is created from the transmission clock. Therefore, the transmitter must be operating even when there is no data to be sent from UARTk to UARTj.
001 : Clock synchronous 0 0 7
TPM
: Internal clock : always "0" Address 3416
!!! : Not used
6
5
4 1
3
2 !
1
0 UART0 transmit/receive control register 0
CPL TxS
CS1 CS2
Clock source selection bits 0 0 : Select f2 0 1 : Select f16 1 0 : Select f64 1 1 : Select f512 ! : Not used 1 : Disable CTS and RTS (I/O port) Data output selection bit 0 : CMOS output 1 : N-channel open-drain output CLK polarity selection bit 0 : In transmitting, transmit data is output at the CLK's falling edge. Not in transmitting, CLK0 level is "H". 1 : In transmitting, transmit data is output at the CLK0's rising edge. Not in transmitting, CLK0 level is "L". Transfer format selection bit 0 : LSB first 1 : MSB first 7 6 5 4 3 2 0 10 UART0 transmit/receive TE control register 1 Address 3516
Trasmit enable flag 0 : Receiving is disabled Fig. 45 Bit configuration of UART0 transmit/receive mode register and UART0 transmit/receive control register 0/1 in the transmission clock output multiple-selection mode
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MI ELI
NA
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ASYNCHRONOUS SERIAL COMMUNICATION (UART)
Asynchronous serial communication can be performed using 7-, 8-, or 9-bit length data. The operation is the same for all data lengths. The following is the description for 8-bit asynchronous communication. With 8-bit asynchronous communication, the bits 2 to 0 of the UARTi transmit/receive mode register must be "101". Bit 3 is used to select an internal clock or an external clock. When bit 3 is "0", an internal clock is selected and when bit 3 is "1", then external clock is selected. When an internal clock is selected, the bit 0 (CS0) and bit 1 (CS1) of UARTi transmit/receive control register 0 are used to select the clock source. When an internal clock is selected for asynchronous serial communication, the CLKi pin can be used as a normal port. When the content of the bit rate generator is n, the selected internal or external clock is divided by (n + 1), then by 16, and passed through a control circuit to create the UART transmission clock or the UART
receive clock. When the selected clock is an internal clock fi or an external clock fEXT, Bit Rate = (fi or fEXT) / {(n + 1) ! 16} Bit 4 selects 1 stop bit or 2 stop bits. The bit 5 is a selection bit of odd parity or even parity. In the odd parity mode, the parity bit is adjusted so that the sum of the 1's in the data and parity bit is always odd. In the even parity mode, the parity bit is adjusted so that the sum of the 1's in the data and parity bit is always even.
(1 / f1 , or 1 / fEXT) ! (n + 1) ! 16 Transmission clock
TEi TIi
CTSi
Write in transmission buffer register Transmission register Transmission buffer register
TENDi TXDi TXEPTY i
Start bit ST D0 D1 D2 D3 D4 D5
Parity bit Stop bit D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Stopped because TEi = "0"
ST D0 D1
Fig. 46 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit is selected
(1 / f1 , or 1 / fEXT) ! (n + 1) ! 16 Transmission clock
TEi TIi
Write in transmission buffer register Transmission register Transmission buffer register
TENDi
Start bit Stop Bit Stop Bit
Stopped because TEi = "0"
TXDi
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1 D2
TXEPTYi Fig. 47 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits is selected
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bit 6 is the parity enable bit which indicates whether to add parity bit or not. Bits 4 to 6 should be set or reset according to the data format of the communicating devices. Bit 7 is the sleep selection bit (refer to the next page). Bit 2 of the UARTi transmit/receive ___ control register 0 is used to ___ ___ determine whether to use CTSi input or RTSi output. CTSi input is used ___ if bit 2 is "0" and RTSi output is used if bit 2 is "1". ___ If CTSi input is selected, the___ can control whether to stop or start user transmission with external___ input. CTSi ___ Whether to use CTS and RTS signals is determined by bit 4 of___ the UART transmit/receive control register 0. Set bit 4 to "0" when CTS ___ and RTS signals ___used, and to "1" when they are not used. ___ are UART2 has the CTS input function, but that does not have the RTS output ___ function (refer to Figure 40.) ___ ___ ___ When CTS and RTS signals are not used, the CTS/RTS pin can be used as ___ a normal port. The following describes the case when the ___ ___ ___ CTS___ RTS signals are used. If CTS and RTS signals are not used, and ___ the CTSi input condition is unnecessary and there is no RTSi output. In addition, output driver format of the transmission data output pin (TXDj), which is CMOS output or N-channel open-drain output, is selected with bit 5 (TXS) of the UARTj transmit/receive control register 0. CMOS output format is selected when bit 5 is "0", and N-channel open-drain output format is selected when bit 5 is "1". When N-channel open-drain output format is selected, make sure to pull-up the data line using a pull-up resistor. However, UART2 does not have bit 5 (TxS) and the format is always CMOS output. In asynchronous serial communication, bits 6 and 7 of the UARTj transmit/receive control register 0 must be "0".
Transmission
Transmission is started when the bit 0 (TEi flag) of UARTi___ transmit/ receive___ control register 1 is "1", the bit 1 (TIi flag) is "0", and CTSi input is "L" if CTSi input is selected. As shown in Figures 46 and 47, data is output from the TXDi pin with the start bit and the stop bit or parity bit specified by the bits 4 to 6 of UARTi transmit/receive mode register. The data is output beginning at the least significant bit. The TIi flag indicates whether the transmission butter is empty or not. It is cleared to "0" when data is written in the transmission buffer and set to "1" when the contents of the transmission buffer register is transferred to the transmission register. When the transmission register becomes empty after the contents has been transmitted, data is transferred automatically from the transmission buffer register to the transmission register if the next transmission start condition is satisfied. ___ Once transmission has started, the TEi flag, TIi flag, and CTSi signal ___ (if CTSi input is selected) are ignored until data transmission is completed. Therefore, transmission does not stop until it completes even if the TEi flag is cleared during transmission. ___ As shown in Figure 46, CTSi input and flags TEi and TIi, which indicate the transmission start condition, are checked while the TENDi signal is "H". Therefore, data can be transmitted continuously if the next transmission data is written in the transmission buffer register and TIi flag is cleared to 0 before the TENDi signal goes "H". The bit 3 (TXEPTYi flag) of the UARTi transmit/receive control register 0 changes to "1" at the next cycle after the TENDi signal goes "H" and changes to "0" when transmission starts. Therefore, this flag can be used to determine whether data transmission is completed. When the TIi flag changes from "0" to "1", the interrupt request bit of the UARTi transmission (transmit/receive in UART2) interrupt control register is set to "1".
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Receive
Receive is enabled when bit 2 (REi flag) of the UARTi transmit/receive control register 1 is set to "1". As shown in Figure 48, the frequency divider circuit at the receiving end begin to work when a start bit is arrived and the data is received. ___ If RTSi output is selected by ___ bit 2 of the UARTi transmit/receive setting control register 0 to "1", the RTSi output is "H" when the REi flag is "0". ___ When the REi flag changes to "1", the RTSi output goes "L" to indicate receive___ and returns to "H" once receive has started. In other ready words, RTSi output can be used to determine externally whether___ the receive register is ready to receive. (UART2 does not have the RTS output function.) The entire transmission data bits are received when the start bit passes the final bit of the receive register of the receive block shown in Figure 38. At this point, the contents of the receive register is transferred to the receive buffer register and the bit 3 of the UARTi transmit/receive control register 1 (RIi flag) is set. In other words, the RIi flag indicates that the receive ___ register contains data when it buffer ___ is set. If RTSi output is selected, RTSi output goes "L" to indicate that the register is ready to receive the next data. The interrupt request bit of the UARTi receive (transmit/receive in UART2) interrupt control register is set when the RIi flag changes from "0" to "1". The bit 4 (OERi flag) of the UARTi transmission control register 1 is set when the next data is transferred from the receive register to the receive buffer register while the RIi flag is "1". In other words when an overrun error occurs. If the OERi flag is "1", it indicates that the next data has been transferred to the receive buffer register before the contents of the receive butter register has been read. Bit 5 (FERi flag) is set when the number of stop bits is less than required (framing error). Bit 6 (PERi flag) is set when a parity error occurs. Bit 7 (SUMi flag) is set when either the OERi flag, FERi flag, or the PERi flag is set. Therefore, the SUMi flag can be used to determine whether there is an error. The setting of the RIi flag, OERi flag, FERi flag, and the PERi flag is
performed while transferring the contents of the receive register to the receive buffer register. The RIi, FERi, and PERi flags are cleared when reading the low-order byte of the receive buffer register or when writing "0" to the REi flag or when setting to be a parallel port. The OERi and SUMi flags are cleared when writing "0" to the REi flag or when the setting to be a parallel port.
Sleep mode
The sleep mode is used to communicate only between certain microcomputers when multiple microcomputers are connected through serial I/O. The sleep mode is entered when bit 7 of the UARTi transmit/receive mode register is set to "1." UART2 does not have the sleep mode. The operation of the sleep mode for an 8-bit asynchronous communication is described below. When sleep mode is selected, the contents of the receive register is not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit asynchronous communication and bit 8 if 9-bit asychronous communication) of the received data is "0". Also the RIi, OERi, FERi, PERi, and the SUMi flag are unchanged. Therefore, the interrupt request bit of the UARTi receive interrupt control register is also unchanged. Normal receive operation takes place when bit 7 of the received data is "1". The following is an example of how the sleep mode can be used. The main microcomputer first sends data with bit 7 set to "1" and bits 0 to 6 set to the address of the subordinate microcomputer which wants to communicate with. Then all subordinate microcomputers receive the same data. Each subordinate microcomputer checks the received data, clears the sleep function selection bit if bits 0 to 6 are its own address and sets the sleep bit if not. Next the main microcomputer sends data with bit 7 cleared. Then the microcomputer with the sleep bit cleared will receive the data, but the microcomputer with the sleep bit set will not. In this way, the main microcomputer is able to communicate only with the designated microcomputer.
fi or fEXT REi Start bit
Check to be "L" level
Stop bit D0
Get data
Start bit
RxDi Receive Clock RIi
D1
D7
Starting at the falling edge of start bit
RTSi
Fig. 48 Receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit is selected
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The A-D converter is an 10-bit successive approximation converter. Figure 49 shows a block diagram of the A-D converter and Figure 50 shows the configuration of the A-D control register 0 (address 1E16) and A-D control register 1 (address 1F16). The frequency of the A-D converter operating clock AD is selected by bit 7 of the A-D control register 0. When bit 7 is "0", AD is the clock frequency divided by 4. That is, AD = f2/4. When bit 7 is "1", AD is the clock frequency divided by 2 and AD = f2/2. The AD during A-D conversion must be 250 kHz or more because the comparator uses a capacity coupling amplifier. Bit 3 of A-D control register 1 is used to select whether to use the conversion result as 10 bits or as 8 bits. The conversion result is used as 10 bits when bit 3 is "1" and as 8 bits when bit 3 is "0". When the conversion result is used as 10 bits, the low-order 8 bits of the conversion result is stored in the even address of the corresponding A-D register and the high-order two bits are stored in bits 0 and 1 of the odd address of the corresponding A-D register. Bits 2 to 7 of the A-D register odd address return "0000002" when read. When the conversion result is used as 8 bits, the high-order 8 bits of the 10-bit A-D conversion are stored in even address of the
corresponding A-D register. In this case, the A-D register odd address returns "0016" when read. The operating mode is selected by bits 3 and 4 of A-D control register 0. The available operating modes are one-shot, repeat, single sweep, repeat sweep. Whether to connect the reference voltage input pin (VREF) with the ladder network or not depends on bit 5 of the A-D control register 1. The VREF pin is connected when bit 5 is "0" and is disconnected when bit 5 is "1" (High impedance state). When A-D conversion is not performed, current from the VREF pin to the ladder network can be cut off by disconnecting ladder network from the VREF pin. Before starting A-D conversion, wait for 1 s or more after clearing bit 5 to "0". The bit of the port direction register corresponding to the analog input pin to be used must be "0" (input mode) because the analog input pin is also used as port P7. Note that when using the sub-clock (XCIN - XCOUT) or UART2, the analog pins shared with those functions cannot be used. The operation of each mode is described below. The interrupt vector and the interrupt control register are common to the A-D conversion interrupt and UART2 transmit/receive interrupt. It is switched by a selection of UART2 function as shown in Figure 37's note.
AD selection
VREF connect selection VREF AVSS
f2
1/2 Vref
1/2
AD
Ladder network
Successive approximation register
A-D control register 1 (1F16) A-D control register 0 (1E16)
Address
Address
A-D register 0 (2116) A-D register 0 (2016) A-D register 1 (2316) A-D register 1 (2216) A-D register 2 (2516) A-D register 2 (2416) A-D register 3 (2716) A-D register 3 (2616) A-D register 4 (2916) A-D register 4 (2816) A-D register 5 (2B16) A-D register 5 (2A16) A-D register 6 (2D16) A-D register 6 (2C16) A-D register 7 (2F16) A-D register 7 (2E16) Data bus (odd) AN0 AN1 AN2 AN3 AN4 AN5/ADTRG AN6 AN7 Selector Data bus (even) Decoder Comparator
Fig. 49 A-D converter block diagram
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) One-shot mode
One-shot mode is selected when bits 3 and 4 of A-D control register 0 are "0". The analog input pin (AN0 - AN7) is selected with bits 0 to 2 of A-D control register 0. A-D conversion can be started by a software trigger or by an external trigger. A software trigger is selected when bit 5 of A-D control register 0 is "0" and an external trigger is selected when it is "1". When a software trigger is selected, A-D conversion is started when bit 6 (A-D conversion start flag) is set to "1". A-D conversion ends after 59 AD cycles and an interrupt request bit of the A-D conversion interrupt control register is set to "1". At the same time, the A-D conversion start flag (bit 6 of the A-D control register 0) is cleared and A-D conversion stops. The result of A-D conversion is stored in the A-D register corresponding to the selected pin. If an external trigger is selected, A-D conversion starts when the A-D ____ conversion start flag is "1" and the ADTRG input changes from "H" to "L". In this case, the pins that can be used for A-D____ conversion are AN0 to AN4, AN6 and AN7 (a total of 7) because the ADTRG pin is also used as the analog voltage input pin (AN5). The operation is the same as with software trigger except that the A-D conversion start flag is not cleared after A-D conversion and a retrigger can be available during A-D conversion. 7 6 5 4 3 2 1 0 A-D control register 0 Address 1E16
(2) Repeat mode
Repeat mode is selected when bit 3 of A-D control register 0 is "1" and bit 4 is "0". The operation of this mode is the same as the operation of one-shot mode except that when A-D conversion of the selected pin is complete and the result is stored in the A-D register, conversion does not stop, but is repeated. No interrupt request is issued in this mode. Furthermore, if software trigger is selected, the A-D conversion start flag is not cleared. The contents of the A-D register can be read at any time.
7
6
5
4 0
3
2
1
0 A-D control register 1
Address 1F16
Analog input selection bits 0 0 0 : Select AN0 0 0 1 : Select AN1 0 1 0 : Select AN2 0 1 1 : Select AN3 1 0 0 : Select AN4 1 0 1 : Select AN5 1 1 0 : Select AN6 1 1 1 : Select AN7 A-D operation mode selection bits 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode Trigger selection bit 0 : Software trigger 1 : ADTRG input trigger A-D conversion start flag 0 : Stop A-D conversion 1 : Start A-D conversion A-D conversion frequency ( 0 : Select f2/4 1 : Select f2/2 Fig. 50 A-D control register bit configuration
AD)
A-D sweep pin selection bits 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 - AN3 (4 pins) 1 0 : AN0 - AN5 (6 pins) 1 1 : AN0 - AN7 (8 pins) 8/10-bit mode selection bit 0 : 8-bit mode 1 : 10-bit mode 0 : Always "0" VREF connection selection bit 0 : VREF is connected 1 : VREF is not connected
selection flag
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Single sweep mode
Single sweep mode is selected when bit 3 of A-D control register 0 is "0" and bit 4 is "1". In the single sweep mode, the number of analog input pins to be swept can be selected. Analog input pins are selected by bits 1 and 0 of the A-D control register 1 (address 1F16). Two pins, four pins, six pins or eight pins can be selected as analog input pins, depending on the contents of these bits. A-D conversion is performed only for selected input pins. After A-D conversion is performed for input of AN0 pin, the conversion result is stored in A-D register 0, and in the same way, A-D conversion is performed for selected pins one after another. After A-D conversion is performed for all selected pins, the sweep is stopped. A-D conversion can be started with a software trigger or with an external trigger input. A software trigger is selected when bit 5 is "0" and an external trigger is selected when it is "1". When a software trigger is selected, A-D conversion is started when A-D control register 0 bit 6 (A-D conversion start flag) is set to "1". When A-D conversion of all selected pins ends, an interrupt request bit of the A-D conversion interrupt control register is set to "1". At the same time, A-D conversion start flag is cleared and A-D conversion stops. If an external trigger is selected, A-D conversion starts when the A-D ____ conversion start flag is "1" and the ADTRG input changes from "H" to "L". In this case, the A-D conversion result which is stored in the A-D ____ register 5 becomes invalid because the ADTRG pin is also used as the AN5 pin. The operation by external trigger is the same as that done by software trigger except that the A-D conversion start flag is not cleared after A-D conversion and a retrigger can be available during A-D conversion.
(4) Repeat sweep mode
Repeat sweep mode 0 is selected when bit 3 of A-D control register 0 is "1" and bit 4 is "1". The difference from the single sweep mode is that A-D conversion does not stop after converting from the AN0 pin to the selected pins, but repeats again from the AN0 pin. The repeat is performed among the selected pins. Also, no interrupt request is generated. Furthermore, if software trigger is selected, the A-D conversion start flag is not cleared. The A-D register can be read at any time.
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdog timer is used to detect unexpected execution sequence caused by software runaway. Figure 51 shows a block diagram of the watchdog timer. The watchdog timer includes a 12-bit binary counter. The watchdog timer counts divided clock f32 or f512. Whether to count f32 or f512 is determined by the watchdog timer frequency selection flag shown in Figure 52. For divided clocks f32 and f512, refer to the section on clock generating circuit. f512 is selected when the flag is "0" and f32 is selected when it is "1". The flag is cleared after reset. "FFF16" is set in the watchdog timer when "L" or 2 Vcc is applied to _____ the RESET pin, STP instruction is executed, data is written to the watchdog timer register, or the most significant bit of the watchdog timer becomes "0". After "FFF16" is set in the watchdog timer, the contents of the watchdog timer is decremented by one at every cycle of f32 or f512. After 2048 counts, the most significant bit of the watchdog timer becomes "0", and a watchdog timer interrupt request bit is set, and "FFF16" is set in the watchdog timer. Normally, a program is written so that data is written in the watchdog timer register before the most significant bit of the watchdog timer becomes "0". If this routine is not executed due to unexpected program runaway, the most significant bit of the watchdog timer becomes eventually "0" and an interrupt is generated. The processor can be reset by setting "1" to the software reset bit (bit 3 of the processor mode register 0) described in Figure 10 on the interrupt section and generating a reset pulse. _____ The watchdog timer stops its function when the RESET pin voltage is raised to double the Vcc voltage. The watchdog timer can also be used to recover from when the clock is stopped by the STP instruction. Refer to the section on stand-by function for more details. The watchdog timer hold the contents during a hold state and the input of the divided clock is stopped. Select with the watchdog timer frequency selection flag.
(If STP instruction is executed, f32 is forced to be selected when the system clock selection bit is "0", or f8 is forced to be selected when the system clock selection bit is "1".)
f32 f512 Watchog timer Hold Write to watchdog timer register
RESET
(Address 6016)
2 * Vcc detection circuit
Set "FFF16"
STP instruction
S R
Q
(Note)
Note. When the main clock external input selection bit is "1" and the main clock or the main clock divided by 8 is selected as a system clock, or the sub-clock external input selection bit is "1" and the sub-clock is selected; the divided clock f16 is input. Fig. 51 Watchdog timer block diagram
7
6
5
4
3
2
1
0
Watchdog timer frequency selection flag
Addresses 6116
0 : Select f512 1 : Select f32
Fig. 52 Watchdog timer frequency selection flag
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
_____
The microcomputer is released from the reset state when the RESET pin is returned to "H" level after holding it at "L" level with the power source voltage at 5 V 10%. Program execution starts at the address formed by setting address A23 - A16 to 0016, A15 - A8 to the contents of address FFFF16, and A7 - A0 to the contents of address FFFE16. Figure 53 shows the status of the internal registers during reset.
Address Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register Port P10 direction register A-D control register 0 A-D control register 1 UART 0 Transmit/Receive mode register UART 1 Transmit/Receive mode register UART 0 transmit/receive control register 0 UART 1 transmit/receive control register 0 UART 0 transmit/receive control register 1 UART 1 transmit/receive control register 1 Count start flag One- shot start flag Up-down flag Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Watchdog timer register
Address
(0416)*** (0516)*** (0816)*** (0916)*** (0C16)*** (0D16)*** (1016)*** (1116)*** (1416)*** (1816)***
0016 0016 0016 0000 0016 0016 0016 0016 0016 0016
Watchdog timer frequency selection flag Memory allocation control UART2 transmit/receive mode register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 Oscillation circuit control register 0 Port function control register Serial transmit control register Oscillation circuit control register 1
A-D/UART2 trans./rece. interrupt control register
(6116)***
0
(6316)*** 0 0 0 0 0 0 0 1 0 (6416)*** (6816)*** 0000000 1000
(6916)*** 0 0 0 0 0 0 1 0 (6C16)*** 0 0 0 0 0 0 0 1 (6D16)*** 0 (6E16)*** (6F16)*** 0 (7016)*** 0016 00 00000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000
(1E16)*** 0 0 0 0 0 ? ? ? (1F16)*** (3016)*** (3816)*** 000 0016 0016 11
UART 0 transmission interrupt control register (7116)*** UART 0 receive interrupt control register
(7216)***
UART 1 transmission interrupt control register (7316)*** UART 1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register
INT0 interrupt control register INT1 interrupt control register INT2/Key input interrupt control register
(7416)*** (7516)*** (7616)*** (7716)*** (7816)*** (7916)*** (7A16)*** (7B16)*** (7C16)*** (7D16)*** (7E16)*** (7F16)***
(3416)*** 0 0 0 0 1 0 0 0 (3C16)*** 0 0 0 0 1 0 0 0 (3516)*** 0 0 0 0 0 0 1 0 (3D16)*** 0 0 0 0 0 0 1 0 (4016)*** (4216)*** (4416)*** (5616)*** (5716)*** (5816)*** (5916)*** (5A16)*** 0016 00000 0016 0016 0016 0016 0016 0016
Processor status register (PS) Program bank register (PG) Program counter (PCH) Program counter (PCL) Direct page register (DPR)
000??0001?? 0016 Contents of FFFF16 Contents of FFFE16 000016 0016
(5B16)*** 0 0 1 0 0 0 0 0 (5C16)*** 0 0 1 (5D16)*** 0 0 1 (5E16)*** (5F16)*** (6016)*** FFF16 0000 0000 0016 0
Data bank register (DT)
Contents of other registers and RAM are undefined during reset. Initialize them by software.
Fig. 53 Microcomputer internal status during reset
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 54 shows an example of a reset circuit. If the stabilized clock is input from the external to the main-clock oscillation circuit, the reset input voltage must be 0.9 V or less when the power source voltage reaches 4.5 V. If a resonator/oscillator is connected to the main-clock oscillation circuit, change the reset input voltage from "L" to "H" after the main-clock oscillation is fully stabilized.
INPUT / OUTPUT PINS
Ports P0 to P8, P10 all have a port direction register and each bit can be programmed for input or output. A pin becomes an output pin when the corresponding bit of the port direction register is set to "1" and an input pin when the bit is cleared to "0". When a pin is programmed for output, the data is written to the port latch and is output, and the contents of the port latch is read instead of the value of the pin. Therefore, a previously output value can be read correctly even when the output "L" voltage is raised by directly driving an LED or others. A pin programmed for input is floating and the value input to the pin can be read. When a pin is programmed for input, the data is written only in the port latch and the pin retains floating. Ports P62 to P64, and P104 to P107, however, have pull-up transistors and the port's pull-up function can be selected by setting "1" to bits 6, 5, 3 of the port function control register (reffer to Figure 11.) A port which corresponds to a port direction register's bit set to "0" is pulled up. A port which corresponds to a bit set to "1" is an output pin and it is not pulled up. Port P9 is output exclusive pin. This becomes floating at reset. The contents are output at finishing data write to the port P9 latch. After that, even when changing the data of the port P9 latch, that port cannot be floating. Figures 55 and 56 show the block diagram of ports P0 to P10 and _ the E pin output format. In the memory expansion mode and the microprocessor mode, ports P0 to P4 are also used as address, data, and control signal pins. Refer to the section on the processor modes for more details.
Power on
VCC
RESET
4.5V 0V
VCC
RESET
0V
0.9V
Note. In this case, stabilized clock is input from the external to the main-clock oscillation circuit. Perform careful evaluation at the system design level before using.
Fig. 54 Example of a reset circuit
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
* Ports P00 - P07, P10 - P17, P20 - P27, P30 - P33, P43 - P46, P100 - P103 (Inside dotted-line not included) Ports P40, P41, P47, P51, P53, P55, P57, P61, P65 - P67, P86 (Inside dotted-line included)
Port direction register
Data bus
Port latch
* Ports P83, P87 (Inside dotted-line not included. Shaded area included.) Ports P50, P52, P54, P56, P60, P82 (Inside dotted-line included. Shaded area not included.) Port P42 (Inside dotted-line not included. Shaded area not included.) N-channel open-drain selection (Note 1)
Port direction register "1"
Output
Note 1. Valid only when pins are used as TxDj pins for serial I/O communication
Data bus
Port latch
* Ports P62 - P64 (Inside dotted-line included.) * Ports P104 - P107 (Inside dotted-line not included.)
Pull-up selection Port direction register
Pull-up transistor
Data bus
Port latch
* Ports P70 - P77
Port direction register
Data bus
Port latch
Analog input
Sub-clock oscillation circuit (Note 2)
Note 2. Only P76, P77 as sub-clock oscillation circuit
_
Fig. 55 Block diagram for ports P0 to P10 and the E pin output format (1)
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
* Ports P80, P81, P84, P85
Port direction register "1" "0"
Output
Data bus
Port latch
* Ports P90, P92 (Inside dotted-line included.) * Ports P94 - P97 (Inside dotted-line not included.)
Output control
Data bus
Port latch
* Port P91 (Inside dotted-line included.) * Port P93 (Inside dotted-line not included.)
Output control Output
Data bus
Port latch
*E
Hold acknowledge "0"
External bus mode (B)
(A)
_
Fig. 56 Block diagram for ports P0 to P10 and the E pin output format (2)
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PROCESSOR MODE
Bits 0 and 1 of processor mode register 0 shown in Figure 57 are used to select any mode of the single-chip mode, the memory expansion mode, the microprocessor mode and the evaluation mode. Ports P0 to P3 and a part of port P4 are used as I/O pins of address, data, and control signals except for in the single-chip mode. As the combination of these address, data, and control signals, either of 2 types (external bus mode A or external bus mode B) can be selected. Figures 58 and 59 show the functions of ports P0 to P4 in each external bus mode. The external memory area changes when the processor mode changes. Figure 60 shows the memory map for each processor mode. Refer to Figure 1 for the addresses of RAM and ROM. The external memory area can be accessed except in the single-chip mode. The accessing of the external memory is affected by the BYTE pin, the wait bit (bit 2 of the processor mode register 0), and the wait selection bit (bit 0 of the processor mode register 1). These will be described next.
* External bus mode
The external bus mode (external bus mode A and external bus mode B) to access an external memory can be selected by the level of the BSEL pin. When the level of the BSEL pin is "H", the external bus mode A (see Figure 58) is selected. When the level of the BSEL pin is "L", the external bus mode B (see Figure 59) is selected.
* BYTE pin
When accessing the external memory, the level of the BYTE pin is used to determine whether to use the data bus as 8-bit width or 16bit width. The data bus has a width of 8 bits when level of the BYTE pin is "H", and port P2 becomes the data I/O pin. The data bus has a width of 16 bits when the level of the BYTE pin is "L", and ports P1 and P2 become the data I/O pins. When accessing the internal memory, the data bus always has a width of 16 bits regardless of the BYTE pin level.
76543210 0 Processor mode register 0
Address 5E16
76543210 Processor mode register 1 Wait selection bit 0 : Wait 0 1 : Wait 1
Address 5F16
Processor mode bit 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Evaluation mode
Wait bit 0 : Wait 1 : No Wait
Software reset bit Reset occurs when this bit is set to "1"
Interrupt priority detection time selection bit 0 0 : Internal clock ! 7 (cycle) 0 1 : Internal clock ! 4 (cycle) 1 0 : Internal clock ! 2 (cycle)
Test mode bit This bit must be "0"
Clock 1 output selection bit 0 : No 1 output 1 : 1 output
Fig. 57 Processor mode register bit configuration
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
[External bus mode A]
PM1 PM0 Port Mode 0 0 Single-chip Mode E Port P0 P07 P00 E BYTE ="L" ~ I/O Port E P07 P00 E P17 P10 Port P1 P17 P10 BYTE ="H" I/O Port ~ E BYTE ="L" P27 ~ Port P2 P20 I/O Port E P27 ~ BYTE ="H" P20 A23~A16 Address Data (even, odd) Same as left E P27 P20 ~ A23~A16 Address Data (even, odd) Ports P4, P5 and their direction registers are treated as 16-bit wide bus. E P33 Port P3 P30 I/O Port ~ E P47 P40 ~ I/O Port P32 P31 P30 E ALE BHE R/W E P47 I/O Port Same as left except for port P42 which outputs 1 independent of bit 7 of the processor mode register 0 (Note) P46 P45 P44 P43 P42 P41 P40
1
0 1 Memory Expansion Mode
1 0 Microprocessor Mode
1 1 Evaluation Chip Mode
(Note)
(Note) Same as left Address A7~A0 Same as left
E P17 P10 ~ E P27 P20 ~ E P33 HLDA Same as left P47 P42 ~ P41 P40 A23~A16 Address
Data (even)
~ ~
A15~A8 Address Data(odd)
Same as left
Same as left
E Address A15~A8 Same as left P17 P10 ~ Same as left A15~A8 Address Data(odd)
Ports P4, P5 and their direction registers are treated as 16-bit wide bus.
Same as left
Same as left
DBC VPA VDA QCL MX
In this case, bit 7 of the processor mode register 0 is "0" Port P4
RDY HOLD
In this case, bit 7 of the processor mode register 0 is "0" P42
1
P42
RDY HOLD
1
Same as above except P42 In this case, bit 7 of the processor mode register 0 is "1"
Same as above except P42 In this case, bit 7 of the processor mode register 0 is "1"
Fig. 58 Relationship between ports P0 to P4 and processor modes (external bus mode A)
_
Note.
The signal output disable selection bit (bit 6 of the oscillation circuit control register 0) can stop the E signal output in the single-chip _ mode and the 1 output in the microprocessor mode. In the memory expansion mode or the microprocessor mode, signal E can also be fixed to "H" when the internal memory area is accessed.
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
[External bus mode B]
PM1 PM0
Mode
0 0 Single-chip mode
E
0 1 Memory expansion mode
(Note 1)
1 0 Microprocessor mode
(Note 1)
Port
E/RDE E
Same as left
(Note 2) RDE E (Note 2)
Port P0
E P00 to P07
I/O Port
P00 to P04 P05 P06 P07
CS0 - CS4 RSMP
Same as left
Address A16, A17
BYTE = "L" Port P1
E
E P10 A8 to A15 to Address P17 E
Same as left
Data(odd)
BYTE = "H"
P10 to P17
I/O Port
P10 to P17 E P20 to P27
Same as left Address A8 to A15
BYTE = "L" Port P2
E
A0 to A7
Address Data(even)
Same as left
BYTE = "H"
P20 to P27
I/O Port
E P20 to P27 E P30
A0 to A7
Address Data (odd,even)
Same as left
E
WEL WEH ALE HLDA
Port P3
P30 to P33
I/O Port
P31 P32 P33
Same as left
(Note 2) E E
Port P4
P40 to P47
P40
HOLD
I/O Port
P41 P42 to P47
RDY
I/O Port
Same as left except for port P4 2 which outputs 1 independent of bit 7 of the processor mode register 0 (Note 2)
* In this case, bit 7 of the processor mode register 0 is "0"
P42
1
* In this case, bit 7 of the processor mode register 0 is "0"
P42
1
Same as above excep t P42 * In this case, bit 7 of the processor mode register 0 is "1"
_ ___
Same as above except P42 * In this case, bit 7 of the processor mode register 0 is "1"
Fig. 59 Relationship between ports P0 to P4, E/RDE pin, and processor modes (external bus mode B) _ Notes 1. In the memory expansion mode or the microprocessor mode, signal E is not output. _ 2. The signal output disable selection bit (bit 6 of the oscillation circuit control register 0) can stop signal E output in the single-chip mode ___ ___ and the 1 output in the microprocessor mode. In the memory expansion mode or the microprocessor mode, signals RDE, WEL, ___ WEH can also be fixed to "H" when the internal memory area is accessed. 3. In the external bus mode B, the evaluation chip mode cannot be selected.
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
* Wait bit
As shown in Figure 61, when the external memory area is accessed with the wait bit (bit 2 of the processor mode register 0 at address 5E16) cleared to "0", the access time can be extended compared with no wait (the wait bit is "1"). The access time is extended in two ways and this is selected with the wait selection bit (bit 0 of the processor mode register 1 at address 5F16). When this bit is "1", the access time is 1.5 times compared to that for no wait. When this bit is "0", the access time is twice compared to that for no wait. At reset, the wait bit and the wait selection bit are "0". The accessing of internal memory area is always performed in the no wait mode regardless of the wait bit. The processor modes are described below.
Internal clock
Port P2
Address
Data Address Data
Wait bit "1" E or RDE, (No wait) WEL,WEH
ALE Access time Port P2
Address
Data
Address
Data
Wait bit "0" E or RDE, WEL,WEH (Wait 1)
ALE Access time Port P2
Address Data Address
Memory expansion mode 0016 SFR 8016
Microprocessor mode
Evaluation chip mode 216 A16 C16 SFR
Wait bit "0" E or RDE, (Wait 0) WEL,WEH
ALE Access time
SFR
Fig. 61 Relationship between wait bit, wait selection bit, and access time
(1) Single-chip mode [00]
RAM RAM RAM
FFF16 100016
ROM
Single-chip mode is entered by connecting the CNVss pin to Vss and starting from reset. Ports P0 to P4 all function as normal I/O ports. Port P42 can output clock 1 by setting bit 7 of the processor mode register 0 to "1". For clock 1, refer to Figure 66. _ _ ___ _ In this mode, signal E is output from pin E/RDE. Signal E output, however, can be stopped by setting the signal output disable selection bit (bit 6 of the oscillation circuit control register 0) to "1", and it is _ possible to switch the E pin function to "L" output. Table 7 shows the function of the signal output disable selection bit.
1FFFF16
(2) Memory expansion mode [01]
Memory expansion mode is entered by setting the processor mode bits to "01" after connecting the CNVss pin to Vss and starting from reset. The function differs between the external bus mode A and the external bus mode B.
FFFFFF16 The shaded area is the external memory area. However, in the external bus mode B, banks 1016 to FF16 cannot be accessed. Additionally, the evaluation chip mode cannot also be selected.
* External bus mode A _ ___
_
_
Fig. 60 External memory area for each processor mode
Pin E/RDE becomes the output pin for signal E. E is an enable signal and is "L" during the data/instruction code read or data write term. When the internal memory area is read or written, _ E can be fixed to "H" by setting the signal output disabe selection bit (bit 6 of the oscillation circuit control register 0) to "1". Port P0 becomes an address output pin and loses its I/O port function. Port P1 has two functions depending on the level of the BYTE pin. In both cases, the I/O port function is lost. When the BYTE pin level is "L", port P1 functions as an address _ _ output pin while E is "H" and as an odd address data I/O pin while E is "L". _ However, if an internal memory is read, external data is ignored while E is "L". When the BYTE pin level "H", port P1 functions as an address output pin.
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
___
___
Port P2 has two functions depending on the level of the BYTE pin. In both cases, the I/O port function is lost. When the BYTE pin level is "L", port P2 functions as an address output pin while E is "H" and as an even address data I/O pin while E is "L". _ However, if an internal memory is read, external data is ignored while E is "L". When the BYTE pin level is "H", port P2 functions as an address _ output pin while E is "H" and as an even and odd address data I/O pin _ while E is "L". However, if an internal memory is read, external data is _ ignored while E is "L". _ ___ ____ Ports P30, P31, P32, and P33 become R/W, BHE, ALE, and HLDA output pin respectively and lose their I/O port functions. _ R/W is a read/write signal which indicates a read when it is "H" and a write when it is "L". ___ BHE is a byte high enable signal which indicates that an odd address is accessed when it is "L". Therefore, two bytes at even and odd addresses are accessed ___ simultaneously when address A0 is "L" and BHE is "L". ALE is an address latch enable signal used to latch the address signal from a multiplexed signal of address and data. The latch is transparent while ALE is "H" to let the address signal pass through and held while ALE is "L". ____ HLDA is a hold acknowledge signal and is used to notify externally ____ when the microcomputer receives HOLD___ and enters hold state. input ____ Ports P40 and P41 become HOLD and RDY input pin, respectively, and lose their output pin function. ____ HOLD is a hold request signal. It is an input signal used to put the ____ microcomputer in hold state. HOLD input is accepted when the internal clock falls from "H" level to "L" level while the bus is not used. Ports P0, P1, P2, P30 and P31 are floating while the microcomputer stays in hold state. These ports become floating after one cycle of ____ internal clock later than HLDA signal changes to "L" level. At releasing hold state, these ports are released from floating state after ____ one cycle of internal clock later than HLDA signal changes to "H" level. ___ RDY is a ready signal. When this signal goes "L", the internal clock ___ stops at "L". RDY is used when a slow external memory is attached. Port P42 becomes a normal I/O port when bit 7 of the processor mode register 0 is "0" and becomes an output___for clock pin 1 when bit 7 is "1". The 1 output is independent of RDY and does not stop ___ even when internal clock stops because of "L" input to the RDY pin.
CSn (n = 0 to 4) to the RDY pin, read/write term for any address areas
* External bus mode B _ ___
___
Pin E/RDE becomes the output pin for RDE. ___ RDE is a read-enable signal and is "L" during the data read term in ___ the read cycle. When the internal memory area is read, RDE can be fixed to "H" by setting the signal output disabe selection bit (bit 6 of the oscillation circuit control register) to "1". Ports P06 and P07 become the output pins for addresses A16 and ____ A17, respectively. Similarly, port P05 becomes the output pin for RSMP, ___ ___ and ports P00 to P04 become the output pins for CS0 to CS4, respectively. In this case, their functions as I/O ports are lost. ___ ___ CS0 to CS4 are the chip select signals and are "L" when the address ____ shown in Table 8 is accessed. RSMP is the ready-sampling signal ___ which is output for the RDY input described later when the external ____ memory area is accessed. By inputting logical AND of RSMP and
can be extended by 1 cycle of clock 1. In addition, the read/write term can also be extended by 2 cycles of clock 1 if the above function and wait 0/1 function specified with the wait bit are used together. Port P1 has two functions depending on the level of the BYTE pin. In bose cases, the I/O port function is lost. When the BYTE pin level___ port P1___ is "L", ___ functions as an address (A15 to A8) output pin while RDE or WEL, WEH are "H" and as an odd ___ ___ ___ address data I/O pin while RDE or WEL, WEH are "L". However, if an ___ internal memory is read, external data is ignored while RDE is "L". When the BYTE pin level is "H", port P1 functions as an address output pin. Port P2 has two functions depending on the level of the BYTE pin. In bose cases, the I/O port function is lost. When the BYTE pin level is "L", ___ P2 functions as an address (A0 port ___ ___ to A7) output pin while RDE or WEL, WEH are "H" and as an even ___ ___ ___ address data I/O pin while RDE or WEL, WEH are "L". However, if an ___ internal memory is read, external data is ignored while RDE is "L". When the BYTE pin level is "H", port P2 functions as an address (A0 ___ ___ ___ to A7) output pin while RDE or WEL, WEH are___and as an even and "H" ___ ___ odd address data I/O pin while RDE or WEL, WEH are "L". However, if ___ an internal memory is read, external data is ignored while RDE is "L". ___ ___ ____ Ports P30, P31, P32, and P33 become WEL, WEH, ALE, and HLDA output pins, respectively and lose their I/O port functions. ___ ___ WEL, WEH are the write-enable low signal and the write-enable high signal, respectively. These signals go "L" during the data write term of the write cycle, but their operations differ depending on the BYTE pin level. ___ In the case the BYTE pin level is "L", WEL is "L" when writing to ___ an even address, WEH is "L" when writing to an odd address, and ___ ___ both WEL and WEH are "L" when writing to even and odd addresses. In the case the ___ pin level is "H", regardless of address, only BYTE ___ ___ ___ WEL is "L", and WEH retains "H". WEL and WEH can also be fixed to ___ "H" when the internal memory is accessed, same as RDE, by writing "1" to the signal output disable selection bit. ALE is an address latch enable signal used to latch the address signal from a multiplexed signal of address and data. The latch is transparent while ALE is "H" to let the address signal pass through and held while ALE is "L". ____ HLDA is a hold acknowledge signal____is used to notify externally and when the microcomputer receives HOLD input and enters into hole state. ____ ___ Ports P40 and P41 become HOLD and RDY input pin, respectively, and lose their output pin function. ____ HOLD is a hold request signal. It is an input signal used to put the ____ microcomputer in hold state. HOLD input is accepted when the internal clock falls from "H" level to "L" level ___ the bus is not used. while _ Ports P0, P1, P2, P30, P31, and pin E/RDE are floating while the microcomputer stays in hold state. These ports become floating after ____ one cycle of internal clock later than HLDA signal changes to "L" level. At releasing hold state, these ports are released ____floating from state after one cycle of internal clock later than HLDA signal changes to "H" level. ___ RDY is a ready signal. If this signal goes "L", the internal clock ___ stops at "L". RDY is used when slow external memory is attached. Port P42 becomes a normal I/O port when bit 7 of the processor
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1 when mode register 0 is "0" and becomes an output___for clock pin bit 7 is "1". The 1 output is independent of RDY and does not stop ___ even when internal clock stops because of "L" input to the RDY pin.
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Microprocessor mode [10]
Microprocessor mode is entered by connecting the CNVss pin to Vcc and starting from reset. It can also be entered by programming the processor mode bits to "10" after connecting the CNVss pin to Vss and starting from reset. This mode (for both the external bus mode A and the external bus mode B) is similar to the memory expansion mode except that internal ROM is disabled and an external memory is required, and clock 1 from port P42 is always output independently of bit 7 of the processor mode register 0. As shown in Table 7, 1 output can also be stopped with the signal output disable selection bit "1". In this case, write "1" to the port P42 direction register.
(4) Evaluation chip mode [11]
Evaluation chip mode can be selected at the external bus mode A only. Evaluation chip mode is entered by applying voltage twice the VCC voltage to the CNVSS pin. This mode is normally used for evaluation tools. _ The functions of E, ports P0 and P3 are the same as those in memory expansion mode. _ Port P1 functions as an address _ output pin while E is "H" and as data I/O pin of odd addresses while E is "L" regardless of the BYTE pin level. _ Port P2 function as an address output pin while E is "H" and as data _ I/O pin of even addresses while E is "L" when the BYTE pin level is "L". When the BYTE pin level is "H" or 2*VCC, port P2 functions as an _ address output pin while E is "H" and as data I/O pin of even and odd _ addresses while E is "L". Port P4 and its data direction register which are located at address 0A16 and 0C16 are treated differently in evaluation chip mode. When these addresses are accessed, the data bus width is treated as 16 bits regardless of the BYTE pin level, and the access cycle is treated as internal memory regardless of the wait bit.
When a voltage twice the VCC voltage is applied to the BYTE pin, the addresses corresponding to the internal ROM area are also treated as 16-bit data bus. The functions of ports P40 and P41 are the same as in memory expansion mode. Ports P42 to P46 become 1, MX, QCL, VDA, and VPA output pins ___ respectively. Port P47 becomes the DBC input pin. 1 from port P42 is always output regardless of bit 7 of processor mode register 0. Signal MX normally contains the contents of flag m, however, the contents of flag x is output when the CPU is using flag x. QCL is the queue buffer clear signal. It becomes "H" when the instruction queue buffer is cleared, for example, when a jump instruction is executed. VDA is the valid data address signal. It becomes "H" while the CPU is reading data from data buffer or writing data to data buffer. It also becomes "H" when the first byte of the instruction (operation code) is read from the instruction queue buffer. VPA is the valid program address signal. It becomes "H" while the CPU is reading an instruction code from the instruction queue buffer. ___ DBC is the debug control signal and is used for debugging. Table 9 shows the relationship between the CNVss pin input level and the processor modes.
Table 9. Relationship between CNVss pin input levels and processor modes CNVss Mode Description Single-chip mode upon * Single-chip * Memory expansion starting after reset. Each mode can be selected by Vss * Microprocessor (* Evaluation chip) changing the processor mode bits by software. Microprocessor mode upon * Microprocessor Vcc (* Evaluation chip) starting after reset. Evaluation chip mode only. 2*Vcc * Evaluation chip Note. In the external bus mode B, the evaluation chip mode cannot be selected.
Table 7. Function of signal output disable selection bit CM6 (bit 6 of oscillation circuit control register 0) CM6 = "1" "L" is output. ___ _ ___ ___ E, RDE, WEL, WEH are output only when the external memory area is accessed. "L" is output after WIT/STP instruction is Memory expansion mode, executed. _ ___ After WIT/STP instruction is executed, Microprocessor mode Standby state selection bit (bit 0 of port E, RDE "H" is output. function control register) must be set to "1". "H"or "L" is output. (Output the content of P42 latch.) Clock 1 is output independent of 1 1 Microprocessor mode output selection bit. Port P42 direction register must be set to "1". Note. Functions shown in Table 7 cannot be emulated in a debugger. For the oscillation circuit control register 0, refer to Figure 64. For the port function control register, refer to Figure 11.
_
Processor mode
Pin
Function CM6 = "0" _ Enable ___ ___ output. signal E is _ ___ E, RDE, WEL, WEH are output when the internal/external memory area is accessed.
Single-chip mode
E ___ ___ ___ _ E, RDE, WEL, WEH
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
___ ___
Table 8. Relationship between access addresses and chip-select signals CS0 to CS4 (external bus mode B) Chip-select signal
___
Area
Access address Memory expansion mode (Note) ----------
CS0
___
CS1
___
CS2
___
CS3
___
CS4
Note.
Microprocessor mode 00 100016 The first half of bank 0016 except to for internal momory area 00 7FFF16 The latter half of bank 0016 except 02 000016 (Note) 00 800016 for internal memory area and to to banks 0116 to 0316. 03 FFFF16 03 FFFF16 04 000016 04 000016 Banks 0416 to 0716 to to 07 FFFF16 07 FFFF16 08 000016 08 000016 Banks 0816 to 0B16 to to 0B FFFF16 0B FFFF16 0C 000016 0C 000016 Banks 0C16 to 0F16 to to 0F FFFF16 0F FFFF16 This applies when both bits 1 and 0 of the memory allocation control register is "0". Refer to on the section ROM AREA MODIFICATION FUNCTION.
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
OSCILLATION CIRCUIT
In the oscillation circuit, two kinds of clock circuits are built-in. One is the main-clock oscillation circuit which uses the XIN and XOUT pins, and the other is the sub-clock (32 kHz) oscillation circuit which uses the XCIN and the XCOUT pins. Either of these two oscillation circuits can output the system clock, and it can be selected. Figure 62 shows the oscillation circuit example with a ceramic resonator or a quartz-crystal oscillator connected. The circuit constants such as capacitance depend on a resonator/oscillator, and these constants shall be set to the resonator/oscillator manufacture's recommended value. Figure 63 shows the example of the external clock input circuit. When inputting the main clock externally, the main-clock oscillation circuit stops operating and power dissipation could be conserved by setting the main clock external input selection bit (bit 1 of the oscillation circuit control register 1, refer to Figure 64) to "1". Note that this bit also has the function to select a return factor from STP state (refer to the section on the STANDBY FUNCTION.) Additionally, write to the oscillation circuit control register 1 as the flow shown in Figure 65. Pins XCIN and XCOUT of the sub-clock oscillation circuit are also used as I/O ports P77 and P76, and these functions are selected with the port-XC selection bit described below. From the time during reset to the time after releasing reset, only the main-clock oscillation circuit operates and the main clock is selected as the system clock. Furthermore, at this time, the sub-clock oscillation circuit stops and pins XCIN and XCOUT become I/O ports (P77, P76). When the port-XC selection bit (bit 4 of the oscillation circuit control register 0) is set to "1" in this condition, I/O ports P77 and P76 are switched to pins XCIN and XCOUT, and then, oscillation starts in the sub-clock oscillation circuit.
XIN
XOUT Left open
XCIN
P76 (P76 as I/O port)
External oscillation circuit Vcc Vss
External oscillation circuit Vcc Vss
* When inputting the main clock externally, set the main clock external input selection bit to "1". Then, leave the XOUT pin open. * When inputting the sub clock externally, set the sub-clock external input selection bit to "1". Then, port P76 becomes an I/O port. Fig. 63 External clock input circuit
When inputting the sub clock externally, set the sub-clock external input selection bit (bit 2 of the oscillation circuit control register 1) to "1" before selecting pins XCIN and XCOUT with the port-Xc selection bit. When the sub-clock external input selection bit is set to "1", port P76 becomes an I/O port (or an analog input AN6). Note that this bit also has the function to select a return factor from STP state (refer to the section on the STANDBY FUNCTION.) When the sub-clock output selection bit (bit 1 of the port function control register, refer to Figure 11) is set to "1" under the condition of the port-Xc selection bit = "1", the sub-clock SUB is output from port P67. Accordingly, the sub-clock 32 kHz can be supplied for external devices.
XIN
Rf
XOUT
XCIN
Rcf
XCOUT
XIN
Rf
XOUT
P77
P76
(P77, P76 as I/O port)
Rd
Rd
(32 kHz)
Rcd
CIN
COUT
CCIN
CCOUT
CIN
COUT
In this case, sub-clock oscillation circuit is used. (Port-Xc selection bit is "1")
In this case, sub-clock oscillation circuit is not used. ( Port-Xc selection bit is "0")
Fig. 62 Oscillation circuit example with external resonator or quartz-crystal oscillator
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
Figures 64 and 66 show the bit configuration of the oscillation circuit control registers 0, 1 and the clock generating circuit diagram. The clock generating circuit consists of main- and sub-clock oscillation circuits, system clock switch circuit, clock dividing circuit, standby control circuit, and others. The oscillation circuit control registers are some of the control registers for the clock generating circuit. Clocks , f2 to f512, fC32, and 1 are used in CPU and internal peripheral devices or are output from pins, and they are made of the main or sub clock, as shown in Figure 66. The system clock and the clock f2 can be switched to high-speed clocks or low-speed clocks shown in Table 10. When using the sub clock, it is possible to select one of 3 types: the main clock divided by 2, the direct main clock (not divided) and the sub clock divided by 2 as the clock f2. When not using the sub clock, it is possible to select one of 4 types: the main clock divided by 2, divided by 8, divided by 16 and the direct main clock (not divided) as the clock f2. This function of clocks switch make it possible to adapt power control to the system operation. Bits 0 to 4 of the oscillation circuit control register 0 and bit 0 of the oscillation circuit control register 1 control sub-clock oscillation start,
system clock selection, stop/restart of main-clock oscillation, subclock drivability selection and the main clock division selection. The method of clocks switch is described bellow. When selecting the main clock as the system clock, the main clock division selection bit (bit 0 of the oscillation circuit control register 1) selects either the main clock divided by 2 or the direct main clock as the clock f2. When this bit is "1", the clock f2 is the direct main clock which is not divided, so that a half external input frequency is enough to perform the same operation speed. Consequently, power dissipation could be conserved (refer to Figure 70.) The main clock division selection bit is valid regardless of either using the sub clock or not. Figure 67 shows the system clock state transition when using the sub clock. From the time during reset to the time reset is released, only the main clock, which is selected as the system clock, oscillates. If the port-XC selection bit is set to "1" in this term, the sub-clock oscillation circuit starts oscillation. When the sub clock is not used, fix the port-XC selection bit to "0" ("0" at reset) and use the P77/AN7 XCIN and P76/AN6/XCOUT pins as I/O ports P77 and P76 or analog inputs AN7 and AN6, respectively.
Table 10. Selection of system clock and clock f2 Sub clock Port-Xc selection bit (CM4) 0 0 0 0 1 1 1 1 System clock selection bit (CM3) 0 0 1 1 0 0 1 1 Main clock division selection bit (CC0) 0 1 0 1 0 1 0 1 System clock Main clock Main clock Main clock divided by 8 Main clock divided by 8 Main clock Main clock Sub clock Sub clock Clock f2 Main clock divided by 2 Main clock Main clock divided by 16 Main clock divided by 8 Main clock divided by 2 Main clock Sub clock divided by 2 Sub clock divided by 2
Not used
Used
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0 CM0 Oscillation circuit control register 0 XCOUT drivability selection bit 0 : LOW 1 : HIGH
CM6 CM5 CM4 CM3 CM2
Address 6C16
Main clock stop bit 0 : Main-clock oscillation is available. 1 : Main-clock oscillation is stopped. System clock selection bit * Port-XC selection bit = "0" (Sub clock is not used.) 0 : Main clock is selected. 1 : Main clock divided by 8 is selected. * Port-XC selection bit = "1" (Sub clock is used.) 0 : Main clock is selected. 1 : Sub clock is selected. Port-Xc selection bit 0 : Ports P77 and P76 are selected. (Sub clock is not used.) 1 : Pins XCIN and XCOUT are selected. (Sub clock is used.) System clock stop bit at wait state 0 : Clocks f2 to f512 are operating at WIT state 1 : Clocks f2 to f512 stop at WIT state Signal output disable selection bit (Refer to Table 7.) 7 6 5 4 0 3 2 1 0 Oscillation circuit control register 1 Main clock division selection bit 0 : Main clock is divided by 2. 1 : Main clock is not divided by 2. Address 6F16 Note. Write to the oscillation circuit control register 1 as the flow shown in Figure 65.
CC2 CC1 CC0
Main clock external input selection bit 0 : Main-clock oscillation circuit is operating by itself. Watchdog timer is used at returning from STP state. 1 : Main-clock is input externally. Watchdog timer is not used at returning from STP state. Sub clock external input selection bit 0 : Sub-clock oscillation circuit is operating by itself. Port P76 functions as XCOUT pin. Watchdog timer is used at returning from STP state. 1 : Sub-clock is input externally. Port P76 functions as I/O port. Watchdog timer is not used ar returning from STP state. X : Not used 0 : Always "0" (However, writing data "5516" shown in Figure 65 is possible.) Clock prescaler reset bit
Fig. 64 Bit configuration of oscillation circuit control registers 0, 1
Writing data "5516" (LDM instruction) Next instruction Writing data "8016" (LDM instruction) Writing data "0Y16" (LDM instruction)
Reset clock prescaler
CC2 to CC0 selection bits
* How to reset clock prescaler
* How to write in CC2 to CC0 selection bits Note. "Y" is the sum of bits to be set. For example, when setting bits 2 and 1 to "1", "Y" becomes "6".
Fig. 65 How to write data in oscillation circuit control register 1
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P76/XCOUT P67/TB2IN/
SUB
P77/XCIN
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1
CM4 CM4 PC1
0
(Oscillation circuit control register 0 : Address 6C16) CM2 : Main clock stop bit CM3 : System clock selection bit CM4 : Port-Xc selection bit CM5 : System clock stop bit at wait state (Oscillation circuit control register 1:Address 6F16) CC0 : Main clock division selection bit CC1 : Main clock external input selection bit CC2 : Sub clock external input selection bit (Port function control register : Address 6D16) PC1 : Sub-clock output selection bit/Timer B2 clock source selection bit
(Port latch) P42/
1 0
Fig. 66 Block diagram of clock generating circuit
1
CM4 CC2 CM3
1
0
PC1 CM4 1/32
1 0
Timer B2 (clock timer) (In event counter mode)
1
Sub clock
1 1 1
fC32 Clock prescaler f2 f16 1/4 1/2 1/2 1/2 f32 1/2 f64 Internal clock 1/8 f512
0 0 0
f8
0
0
XOUT 1/8 System clock CM4 CC0 CM3 CM3 CM4
XIN
0
1
Main clock
CM2 CM3
WDC
12-bit Watchdog timer Watchdog timer frequency selection flag
1
CC1 CM5 S STP instruction WIT instruction R Q Q S R STP instruction
Q
S
Reset
0
CC1 CM3 CM4 Interrupt disable flag Interrupt request CC2
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Main clock : Oscillating WIT instruction Sub clock : Stopped I/O ports P77 and P76 f2 : Main-clock side Interrupt (Note 2) : Stopped
Main clock : Oscillating Sub clock : Stopped I/O ports P77 and P76 f2 : Main-clock side : Main-clock side
STP instruction
Interrupt
Main clock : Stopped Sub clock : Stopped I/O ports P77 and P76 f2 : Stopped : Stopped
XC is selected (CM4 = "1")
Main clock : Oscillating Sub clock : Oscillating f2 : Main-clock side (Note 2) : Stopped
WIT instruction
Interrupt
Main clock : Oscillating Sub clock : Oscillating f2 : Main-clock side : Main-clock side
STP intrunction
Interrupt
Main clock : Stopped Sub clock : Stopped f2 : Stopped : Stopped
Main clock is selected as system clock (Note 1) (CM3 = "0")
Sub clock is selected as system clock (Note 1) (CM3 = "1")
WIT instruction Main clock : Oscillating Sub clock : Oscillating f2 : Sub-clock side (Note 2) Interrupt : Stopped
Main clock : Oscillating Sub clock : Oscillating f2 : Sub-clock side : Sub-clock side
STP intrunction
Interrupt
Main clock : Stopped Sub clock : Stopped f2 : Stopped : Stopped
Main clock oscillation starts (CM2 = "0")
Main clock oscillation stops (CM2 = "1")
WIT instruction Main clock :Stopped Sub clock :Oscillating f2 : Sub-clock side (Note 2) : Stopped Interrupt
Main clock : Stopped Sub clock : Oscillating f2 : Sub-clock side : Sub-clock side
STP instruction
Interrupt
Main clock : Stopped Sub clock : Stopped f2 : Stopped : Stopped
Notes1. Before selecting the main/sub clock of which oscillation already starts as the system clock, use software to fully stabilize the oscillation. 2. When the system clock stop bit at wait state (CM 5 ) is "1", f 2 stops at wait state.
Fig. 67 System clock state transition
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 68 shows the system clock selection change example when using the sub clock. When the system clock selection bit is "1" after sub-clock oscillation starts, the sub clock is selected as the system clock. Make sure to select the sub clock after the sub-clock oscillation is fully stabilized. When the main clock stop bit is set to "1" after the sub clock is selected, the main-clock oscillation/input stops. By stopping the main-clock oscillation, current consumption can be further restricted. When the main clock stop bit is cleared to "0" after the main-clock oscillation stops, the main-clock oscillation/input restarts. When the system clock selection bit is "0" after the main-clock oscillation restarts, the main clock is selected as the system clock again. Make sure to select the main clock after the main-clock oscillation restarts and is fully stabilized. The XCOUT drivability selection bit is a bit to select the drivability of the sub-clock oscillation circuit and is set to "1" (HIGH) after reset is released. Make sure to clear the XCOUT drivability selection bit to "0" (LOW) after the sub-clock oscillation is fully stabilized. Note that the port-XC selection bit cannot be cleared by software when it is once set to "1". The bit can be cleared only by reset. It is impossible to write "1" to the port-XC selection bit and the system clock selection bit at the same time. In addition, the contents of the main clock stop bit and the XCOUT drivability selection bit cannot be changed when the port-XC selection bit is "0".
Port-Xc selection bit (CM4)
System colck selection bit (CM3)
Main clock stop bit (CM2)
Main clock
Sub clock
Main clock
System clock
Oscillation stabilizing time
Main-clock oscillation
Stopped Operating Oscillation stabilizing time Operating
Sub-clock oscillation
Stop
Operating
Fig. 68 System clock selection change example
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When the port-XC selection bit is set to "1" to use sub-clock oscillation and timer B2 is set to be in the event count mode, clock fC32 which is the sub clock (32 kHz) divided by 32 is selected as the count source of timer B2. By this selection, timer B2 can be used as the clock timer. For setting of timer B2 related registers, refer to the section on clock timer mode of timer B2. The clock prescaler in which the sub clock is divided by 32 is reset by writing "1", in dummy, into bit 7 (clock prescaler reset bit) of the oscillation circuit control register 1. When the main clock is selected, by this function, clock fC32 of clock timer B2 can be synchronized with software. Figure 69 shows the operation timing for clock prescaler and clock timer B2. Figure 70 shows the clock f2 state transition when the port-Xc selection bit is "0" and the sub clock is not used.
From the time during reset to the time reset is released, the main clock divided by 2 is being selected as the clock f2. When the system clock selection bit is set "1" in that condition, the main clock divided by 16 is selected as the clock f2 and the clock frequency supplied for the CPU and internal peripheral devices is divided by 8 more. It makes current consumption restrict, although the operation speed slows. When the timer B2 clock source selection bit (bit 1 of the port function control register) is set to "1" and event counter mode is selected in timer B2 under the condition which the port-Xc selection bit is "0"; fc32, which is the main clock divided by 32, is connected as a timer B's count source. Accordingly, timer B2 can be used as a clock timer which always operates with a regular clock source shown in Figure 70. For details relating to register setting of timer B2, refer to the section "Clock timer" on timer B.
Timer B2 count start flag
Writing pulse of clock prescaler reset bit XCIN XCIN x 31(cycle)
(Note)
XCIN x 32 (cycle)
Clock source of clock timer(fc32)
Timer B2 count value
n (Set value)
n-1
This applies when the main clock is selected as the system clock (System clock selection bit (CM3) = "0"). Note. Period of fc32 = XCIN x 31 (cycle) (only in this term) Period of fc32 = XCIN x 32 (cycle) (after this term) Fig. 69 Operation timing for clock prescaler and clock timer B2
Reset
(Note 1)
Notes 1. f2 = f(XIN) / 2 expresses that the clock f2 is the main clock divided by 2. 2. f2 = f(XIN) expresses that the clock f2 is the direct main clock, which is not divided. CM3 = "0"
f2 = f(XIN) / 2 CC0 = "1" CC0 = "0"
(Note 1) 2)
CM3 = "1" f2 = f(XIN) / 16
= f(XIN) / f2f2 = f(XIN) 2 CM3 = "0" CM3 = "1" f2 = f(XIN) / 8 * In the case of not using sub clock (CM4 = "0") Fig. 70 Clock f2 state transition (when the sub clock is not used.) CC0 = "1" CC0 = "0"
CC0 = Main clock division selection bit CM3 = System clock selection bit CM4 = Port-Xc selection bit
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
STANDBY FUNCTION
The WIT and the STP instructions make the microcomputer standby state. Table 11 shows the relationship between standby state and each block's operation. When the WIT instruction is executed with the system clock stop bit at wait state (bit 5 of the oscillation circuit control register 0) = "0", internal clock is stopped being at "L", but the oscillation circuit, system clock, and divided clocks f2 to f512 are not stopped. Because divided clocks f2 to f512 are not stopped, a part of internal peripheral devices which use these divided clocks can operate even at wait state. Otherwise, when the WIT instruction is executed with the system clock stop bit at wait state = "1", the oscillation circuit is not stopped, but the system clock, divided clocks, and internal clock are stopped. Accordingly, in this case, all of the internal peripheral devices which use divided clocks f2 to f512, including the watchdog timer, are stopped. When port-XC selection bit is "1" to operate the sub-clock oscillation circuit, however, clock timer B2 can operate because clock fC32 for the clock timer is not stopped. When internal peripheral devices are not used, later wait state (System clock stop bit at wait state = "1") is more effective to restrict the current consumption. Make sure to set the system clock stop bit at wait state to "1" immediately before the WIT instruction execution and clear the bit to "0" immediately after the wait state is terminated. The wait state is terminated when an interrupt request is accepted, and the internal clock operation is restarted. At this time, interrupt processing can immediately be executed because oscillation circuit's operation is not stopped during the wait state. When the STP instruction is executed, the oscillation circuit is stopped with internal clock stopped at "L". Furthermore, "FFF16" is automatically set into the watchdog timer, and the clock source of
the watchdog timer is forced to connect with f32 when the main clock is selected or f8 when the sub clock is selected. This connection is cut off when the most significant bit of the watchdog timer is cleared to "0" or the microcomputer is reset, and the clock source is connected with the input depending on the content of the watchdog timer frequency selection flag. In the stop state, internal peripheral devices using divided clocks f2 to f512 are stopped. The stop state is terminated by system reset or interrupt request acceptance, and then oscillation is restarted. At this time, supply of system clock and divided clocks f2 to f512 is restarted. In that condition, when the main clock external input selection bit is "0" and the main clock is being selected as a system clock, or when the sub clock external input selection bit is "0" and the sub clock is being selected as a system clock, internal clock is stopped at "L" till the most significant bit of the watchdog timer decremented with divided clock f32 or f8 becomes "0". However, supply of internal clock is restarted immediately after the oscillation restarts by reset. Accordingly, in this case, it is necessary to wait for the oscillation stabilized before making the reset input "H". Otherwise in that condition, when the main clock external input selection bit is "1" and the main clock is being selected as a system clock, or when the sub clock external input selection bit is "1" and the sub clock is being selected as a system clock, supply of internal clock is restarted from the seventh clock of clock f2 after the oscillation restarts. By this function, the microcomputer can immediately return from the stop state when the clock supply input from the external is stabilized. Even though the main clock or the sub clock is input externally, make sure to clear the main clock external input selection bit or the sub clock external input selection bit to "0" before executing the STP instruction if this external clock is unstable for a short time at a return from the stop state.
Table 11. Relationship between standby state and each block's operation Instruction System clock stop bit at wait Oscillation circuit state
"0" WIT "1" STP -- Operating (Note) Operating (Note) Stopped
Operation at WIT/STP state
System clock Operating Stopped Stopped f2 - f512 Operating Stopped Stopped Clock output Operating Stopped ("L") Stopped ("L")
1
Internal clock Stopped ("L") Stopped ("L") Stopped ("L")
Internal peripheral devices using f2 - f512 Operation enabled (Watchdog timer is operating) Operation disabled (Watchdog timer is stopped) (Clock timer's operation is enabled) Operation disabled (Watchdog timer is stopped)
Note. When the main clock external input selection bit is "1", the main clock oscillation circuit stops. When the sub clock external input selection bit is "1", the sub-clock oscillation circuit stops. (In both cases, the external clock can be input.)
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The wait/stop state is terminated by interrupt acceptance or reset. Accordingly, it is necessary to prepare the state in which any interrupt can be accepted before the WIT/STP instruction is executed. Additionally, it is necessary to set the system clock stop bit at wait state before the WIT instruction is executed. When the WIT/STP instruction is executed in a bus access cycle, the _ ___ ___ ___ bus enters the non-access state (E, RDE, WEL, WEH are at "H") because internal clock (or oscillation) ___ is stopped ____ the read/ after write in this cycle is finished. Pins P00/A0/CS0 to P33/HLDA normally retain the state at which internal clock is stopped in the wait/stop state. However, only in the memory expansion mode and the microprocessor mode, arbitrary data which is set in the port P0 to P3 latches can be ___ ____ output from pins P00/A0/CS0 to P33/HLDA even at the wait/stop state when the following conditions are satisfied before the WIT/STP instruction execution. * The standby state selection bit (bit 0 of the port function control register) is set to "1". * "FF16" is set into the port P0 to P3 direction registers. Furthermore, when the standby state selection bit is set to "1" and bit 6 of the oscillation circuit control register 0 (signal output ___ disable _ selection bit) is set to "1", "L" level can be output from the E/RDE pin at the wait/stop state. For the signal output disable selection bit, refer to Table 7 on the processor mode section. Note that the function of arbitrary data output cannot be emulated using a debugger.
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ROM AREA MODIFICATION FUNCTION
The internal ROM size and RAM size of the M37736MHBXXXGP can be modified by the memory allocation control register's bits 0,1 and 2 shown in Figure 71. Figure 73 shows the memory allocation in which the internal ROM size and RAM size are modified. Make sure to write data in the memory allocation control register as the flow shown in Figure 72. This ROM area modification function is valid in memory expansion mode and single-chip mode. Table 12 shows the relationship between the memory allocation
selection bits and addresses corresponding to chip-select signals ___ ___ CS0 and CS1 in the memory expansion mode with the external bus mode B. When ordering a mask ROM, Mitsubishi Electric corp. produces the mask ROM using the data within 128 Kbytes (addresses 00000016 - 01FFFF16). It is regardless of the selected ROM size (refer to MASK ROM ORDER CONFIRMATION FORM.) Therefore, program "FF16" to the addresses out of the selected ROM area in the EPROM which you tender when ordering a mask ROM. Address 01FFFF16 of this microcomputer corresponds to the lowest address of the EPROM which you tender.
7
6
5
4 0
3 0
2 ML2
1 ML1
0 ML0 Memory allocation control register
Address 6316
Memory allocation selection bits ROM size RAM size 0 0 0 : 124 Kbytes 3968 bytes 0 0 1 : 120 Kbytes 3968 bytes 0 1 0 : 60 Kbytes 2048 bytes 1 0 0 : 32 Kbytes 2048 bytes 1 0 1 : 16 Kbytes 2048 bytes 1 1 0 : 96 Kbytes 3968 bytes 0 0 : Always "00" (However, writing data "5516" shown in Figure 72 is possible.)
Note. Write to the memory allocation control register as the flow shown in Figure 72. Fig. 71 Bit configuration of memory allocation control register
Writing data "5516" (LDM instruction) Next instruction Writing data "0Y16" (LDM instruction)
ML2, ML1, ML0 selection bits * How to write in memory allocation control register
Note. "Y" is the sum of bits to be set. For example, when setting bit 1 to "1", "Y" becomes "2". Fig. 72 How to write data in memory allocation control register Table 12 Relationship between memory allocation selection bits and addresses corresponding to chip-select signals CS0 and CS1 in memory expansion mode (external bus mode B) Memory allocation selection bits Access addresses Internal ROM area ML2 ML1 ML0 CS0 CS1 0 0 0 00100016 - 01FFFF16 ------------ 02000016 - 03FFFF16 0 0 1 00200016 - 01FFFF16 00100016 - 001FFF16 02000016 - 03FFFF16 0 1 0 00100016 - 00FFFF16 00088016 - 000FFF16 01000016 - 03FFFF16 1 0 0 00800016 - 00FFFF16 00088016 - 007FFF16 01000016 - 03FFFF16 00800016 - 00BFFF16 1 0 1 00C00016 - 00FFFF16 00088016 - 007FFF16 01000016 - 03FFFF16 1 1 0 00800016 - 01FFFF16 00100016 - 007FFF16 02000016 - 03FFFF16
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(ML2, ML1, ML0) = (0, 0, 0) 00000016 00007F16 00008016 000FFF16 00100016 SFR Internal RAM 3968 bytes
(ML2, ML1, ML0) = (0, 0, 1) 00000016 00007F16 00008016 000FFF16 00200016 SFR Internal RAM 3968 bytes
(4 Kbytes)
(ML2, ML1, ML0) = (0, 1, 0) 00000016 00007F16 00008016 00087F16 00100016 Internal ROM 60 Kbytes 00FFFF16 01000016 SFR Internal RAM 2048 bytes
(1.9 Kbytes)
00FFFF16 01000016
Internal ROM 124 Kbytes
00FFFF16 01000016
Internal ROM 120 Kbytes
01FFFF16
01FFFF16
FFFFFF16
FFFFFF16
FFFFFF16
(ML2, ML1, ML0) = (1, 0, 0) 00000016 00007F16 00008016 00087F16 SFR Internal RAM 2048 bytes (29.9 Kbytes) 00800016 Internal ROM 32 Kbytes 00FFFF16 01000016
(ML2, ML1, ML0) = (1, 0, 1) 00000016 00007F16 00008016 00087F16 SFR Internal RAM 2048 bytes (45.9 Kbytes)
(ML2, ML1, ML0) = (1, 1, 0) 00000016 00007F16 00008016 000FFF16 00800016 SFR Internal RAM 3968 bytes (28 Kbytes)
00C00016 00FFFF16 01000016
Internal ROM 16 Kbytes
00FFFF16 01000016
Internal ROM 96 Kbytes
01FFFF16
FFFFFF16
FFFFFF16
FFFFFF16
: External memory area
Note. In the external bus mode B, banks 1016 to FF16 cannot be accessed. Fig. 73 Memory allocation (modification of internal ROM and RAM area by memory allocation selection bits)
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ADDRESSING MODES
The M37736MHBXXXGP has 28 powerful addressing modes. Refer to the "7700 Family Software Manual" for the details.
MACHINE INSTRUCTION LIST
The M37736MHBXXXGP has 103 machine instructions. Refer to the "7700 Family Software Manual" for the details.
DATA REQUIRED FOR MASK ROM ORDERING
Please send the following data for mask orders. (1) M37736MHBXXXGP mask ROM order confirmation form (2) 100P6S mark specification form (3) ROM data (EPROM 3 sets)
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc AVcc VI Parameter Conditions Power source voltage Analog power source voltage _____ Input voltage RESET, CNVss, BYTE Input voltage P00 - P07, P10 - P17, P20 - P27, P30 - P33, P40 - P47, P50 - P57, P60 - P67, P70 - P77, P80 - P87, P90 - P92, P100 - P107, VREF, XIN, BSEL Output voltage P00 - P07, P10 - P17, P20 - P27, P30 - P33, P40 - P47, P50 - P57, P60 - P67, P70 - P77, P80 - P87, _ P90 - P97, P100 - P107, XOUT, E Power dissipation Ta = 25 C Operating temperature Storage temperature Ratings -0.3 to +7 -0.3 to +7 -0.3 to +12 Unit V V V
VI
-0.3 to Vcc + 0.3
V
VO Pd Topr Tstg
-0.3 to Vcc + 0.3 300 -20 to +85 - 40 to +150
V mW C C
RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V 10%, Ta = -20 to +85 C, unless otherwise noted)
Symbol Vcc AVcc Vss AVss VIH VIH VIH VIL VIL VIL IOH(peak) Power source voltage Parameter f(XIN) : Operating f(XIN) : Stopped, f(XCIN) = 32.768 kHz Analog power source voltage Power source voltage Analog power source voltage High-level input voltage P00 - P07, P30 - P33, P40 - P47, P50 - P57, P60 - P67, _____ P70 - P77, P80 - P87, P90 - P92, P100 - P107, XIN, RESET, CNVss, BYTE, BSEL, XCIN (Note 3) High-level input voltage P10 - P17, P20 - P27 (in single-chip mode) High-level input voltage P10 - P17, P20 - P27 (in memory expansion mode and microprocessor mode) Low-level input voltage P00 - P07, P30 - P33, P40 - P47, P50 - P57, _____ P60 - P67, P70 - P77, P80 - P87, P90 - P92, P100 - P107, XIN, RESET, CNVss, BYTE, BSEL, XCIN (Note 3) Low-level input voltage P10 - P17, P20 - P27 (in single-chip mode) Low-level input voltage P10 - P17, P20 - P27 (in memory expansion mode and microprocessor mode) High-level peak output current P00 - P07, P10 - P17, P20 - P27, P30 - P33, P40 - P47, P50 - P57, P60 - P67, P70 - P77, P80 - P87, P90 - P97, P100 - P107 High-level average output current P00 - P07, P10 - P17, P20 - P27, P30 - P33, P40 - P47, P50 - P57, P60 - P67, P70 - P77, P80 - P87, P90 - P97, P100 - P107 Low-level peak output current P00 - P07, P10 - P17, P20 - P27, P30 - P33, P40 - P43, P54 - P57, P60 - P67, P70 - P77, P80 - P87, P90 - P97, P104 - P107 Low-level peak output current P44 - P47, P100 - P103 Low-level average output current P00 - P07, P10 - P17, P20 - P27, P30 - P33, P40 - P43, P54 - P57, P60 - P67, P70 - P77, P80 - P87, P90 - P97, P104 - P107 Low-level average output current P44 - P47, P100 - P103 Main-clock oscillation frequency (Note 4) Sub-clock oscillation frequency Min. 4.5 2.7 Limits Typ. 5.0 Vcc 0 0 0.8 Vcc 0.8 Vcc 0.5 Vcc 0 0 0 Vcc Vcc Vcc 0.2Vcc 0.2Vcc 0.16Vcc -10 Max. 5.5 5.5 Unit V V V V V V V V V V mA
IOH(avg)
-5
mA
IOL(peak) IOL(peak) IOL(avg) IOL(avg) f(XIN) f(XCIN)
10 20 5 15 25 50
mA mA mA mA MHz kHz
32.768
Notes 1. Average output current is the average value of a 100 ms interval. 2. The sum of IOL(peak) for ports P0, P1, P2, P3, P8, and P9 must be 80 mA or less, the sum of IOH(peak) for ports P0, P1, P2, P3, P8, and P9 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, P7, and P10 must be 100 mA or less, and the sum of IOH(peak) for ports P4, P5, P6, P7, and P10 must be 80 mA or less. 3. Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = "1". 4. The maximum value of f(XIN) = 12.5 MHz when the main clock division selection bit = "1".
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz, unless otherwise noted)
Symbol Parameter Test conditions Min. 3 Limits Typ. Max. Unit High-level output voltage P00 - P07, P10 - P17, P20 - P27, P33, P40 - P47, P50 - P57, IOH = -10 mA P60 - P67, P70 - P77, P80 - P87, P90 - P97, P100 - P107 High-level output voltage P00 - P07, P10 - P17, P20 - P27, IOH = -400 m A P33 IOH = -10 mA High-level output voltage P30 - P32 ICH = -400 m A _ IOH = -10 mA High-level output voltage E IOH = -400 m A Low-level output voltage P00 - P07, P10 - P17, P20 - P27, P33, P40 - P43, P50 - P57, IOL = 10 mA P60 - P67, P70 - P75, P80 - P87, P90 - P97, P104 - P107 Low-level output voltage P44 - P47, P100 - P103 IOL = 20 mA Low-level output voltage P00 - P07, P10 - P17, P20 - P27, IOL = 2 mA P33 IOL = 10 mA Low-level output voltage P30 - P32 IOL = 2 mA _ IOL = 10 mA Low-level output voltage E IOL = 2 mA ____ ___ Hysteresis ___ ___ ____ - TA4IN, TB0IN - TB2IN, HOLD, RDY, TA0IN ___ ___ ___ INT0 - INT2, ADTRG, __ CTS0, CTS1, CTS2, CLK0, __ CLK1, CLK2, KI0 - KI3 _____ Hysteresis RESET Hysteresis XIN Hysteresis XCIN (When external clock is input) High-level input current P00 - P07, P10 - P17, P20 - P27, P30 - P33, VI = 5 V P40 - P47, P50 - P57, P60 - P67, P70 - P77, _____ P80 - P87, P90 - P92, P100 - P107, XIN, RESET, CNVss, BYTE, BSEL Low-level input current P00 - P07, P10 - P17, P20 - P27, P30 - P33, VI = 0 V P40 - P47, P50 - P57, P60, P61, P65 - P67, P70 _____ P80 - P87, P90 - P92, P100 - P103, - P77, XIN, RESET, CNVss, BYTE, BSEL VI = 0 V, Low-level input current P104 - P107, P62 - P64
without a pull-up transistor
VOH
V
VOH VOH VOH
4.7 3.1 4.8 3.4 4.8 2 2 0.45 1.9 0.43 1.6 0.4 0.4 0.2 0.1 0.1 1 0.5 0.4 0.4
V V V
VOL VOL VOL VOL VOL
V V V V V V V V V
VT+ - VT- VT+ - VT- VT+ - VT- VT+ - VT-
IIH
5
mA
IIL
-5
mA
-5 -0.25 2 -0.5 -1.0
IIL
mA
mA V
VRAM
RAM hold voltage
VI = 0 V, with a pull-up transistor When clock is stopped.
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = -20 to 85 C, unless otherwise noted)
Symbol Parameter Test conditions VCC = 5 V, f(XIN) = 25 MHz (square waveform), f(f2) = 12.5 MHz, f(XCIN) = 32.768 kHz, in operating (Note 1) VCC = 5 V, f(XIN) = 25 MHz (square waveform), (f(f2) = 1.5625 MHz), f(XCIN) = Stopped, in operating (Note 1) Power source current In single-chip mode, output pins are open, and other pins are VSS. VCC = 5V, f(XIN) = 25 MHz (square waveform), f(XCIN) = 32.768 kHz, when a WIT instruction is executed (Note 2) VCC = 5 V, f(XIN) : Stopped, f(XCIN) : 32.768 kHz, in operating (Note 3) VCC = 5 V, f(XIN) : Stopped, f(XCIN) : 32.768 kHz, when a WIT instruction is executed (Note 4) Ta = 25 C, when clock is stopped Ta = 85 C, when clock is stopped Min. Limits Typ. Max. Unit
9.5
19
mA
1.3
2.6
mA
ICC
10
20
mA
50
100
mA
5
10
mA
1 20
mA mA
Notes 1. This applies when the main clock external input selection bit = "1", the main clock division selection bit = "0", and the signal output stop bit = "1". 2. This applies when the main clock external input selection bit = "1" and the system clock stop bit at wait state = "1". 3. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4. This applies when the XCOUT drivability selection bit = "0" and the system clock stop bit at wait state = "1".
A-D CONVERTER CHARACTERISTICS
(VCC = AVCC = 5 V, VSS = AVSS = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz (Note), unless otherwise noted) Symbol Parameter Test conditions Min. Limits Typ. Max. 10 3 25 VCC VREF Unit Bits LSB k ms V V
-- Resolution VREF = VCC -- Absolute accuracy VREF = VCC RLADDER Ladder resistance VREF = VCC tCONV Conversion time VREF Reference voltage VIA Analog input voltage Note. This applies when the main clock division selection bit = "0" and f(f2) = 12.5 MHz.
10 9.44 2 0
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS (VCC = 5 V 10%, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz, unless otherwise noted (Note))
Notes 1. This applies when the main clock division selection bit = "0" and f(f2) = 12.5 MHz. 2. Input signal's rise/fall time must be 100 ns or less, unless otherwise noted.
External clock input
Symbol Parameter Limits Min. 40 15 15 Max. Unit
tc External clock input cycle time (Note 3) ns tw(H) External clock input high-level pulse width (Note 4) ns tw(L) External clock input low-level pulse width (Note 4) ns tr External clock rise time 8 ns tf External clock fall time 8 ns Notes 3. When the main clock division selection bit = "1", the minimum value of tc = 80 ns. 4. When the main clock division selection bit = "1", values of tw(H) / tc and tw(L) / tc must be set to values from 0.45 through 0.55.
Single-chip mode
Symbol tsu(P0D-E) tsu(P1D-E) tsu(P2D-E) tsu(P3D-E) tsu(P4D-E) tsu(P5D-E) tsu(P6D-E) tsu(P7D-E) tsu(P8D-E) tsu(P10D-E) th(E-P0D) th(E-P1D) th(E-P2D) th(E-P3D) th(E-P4D) th(E-P5D) th(E-P6D) th(E-P7D) th(E-P8D) th(E-P10D) Port P0 input setup time Port P1 input setup time Port P2 input setup time Port P3 input setup time Port P4 input setup time Port P5 input setup time Port P6 input setup time Port P7 input setup time Port P8 input setup time Port P10 input setup time Port P0 input hold time Port P1 input hold time Port P2 input hold time Port P3 input hold time Port P4 input hold time Port P5 input hold time Port P6 input hold time Port P7 input hold time Port P8 input hold time Port P10 input hold time Parameter Limits Min. 60 60 60 60 60 60 60 60 60 60 0 0 0 0 0 0 0 0 0 0 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Memory expansion mode and microprocessor mode
Symbol tsu(D-E) tsu(D-RDE) tsu(RDY- 1) tsu(HOLD- 1) th(E-D) th(RDE-D) th( 1-RDY) th( 1-HOLD) Parameter Data input setup time (external bus mode A) Data input setup time (external bus mode B) ___ RDY input setup time ____ HOLD input setup time Data input hold time (external bus mode A) Data input hold time (external bus mode B) ___ RDY input hold time ____ HOLD input hold time Limits Min. 32 32 55 55 0 0 0 0 Max. Unit ns ns ns ns ns ns ns ns
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A input
Symbol tc(TA) tw(TAH) tw(TAL)
(Count input in event counter mode) parameter Limits Min. 80 40 40 Max. Unit ns ns ns
TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width
Timer A input (Gating input in timer mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time (Note) TAiIN input high-level pulse width (Note) TAiIN input low-level pulse width (Note) parameter Limits Min. 320 160 160 Max. Unit ns ns ns
Note. Limits change depending on f(XIN). Refer to "DATA FORMULAS" on page 75.
Timer A input (External trigger input in one-shot pulse mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time (Note) TAiIN input high-level pulse width TAiIN input low-level pulse width parameter Limits Min. 320 80 80 Max. Unit ns ns ns
Note. Limits change depending on f(XIN). Refer to "DATA FORMULAS" on page 75.
Timer A input (External trigger input in pulse width modulation mode)
Symbol tw(TAH) tw(TAL) TAiIN input high-level pulse width TAiIN input low-level pulse width parameter Limits Min. 80 80 Max. Unit ns ns
Timer A input (Up-down input in event counter mode)
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time parameter Limits Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns
Timer A input (Two-phase pulse input in event counter mode)
Symbol tc(TA) TAj input cycle time tsu(TAjIN-TAjOUT) TAjIN input setup time tsu(TAjOUT-TAjIN) TAjOUT input setup time parameter Limits Min. 800 200 200 Max. Unit ns ns ns
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B input (Count input in event counter mode)
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edges count) TBiIN input high-level pulse width (both edges count) TBiIN input low-level pulse width (both edges count) Limits Min. 80 40 40 160 80 80 Max. Unit ns ns ns ns ns ns
Timer B input (Pulse period measurement mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time (Note) TBiIN input high-level pulse width (Note) TBiIN input low-level pulse width (Note) Parameter Limits Min. 320 160 160 Max. Unit ns ns ns
Note. Limits change depending on f(XIN). Refer to "DATA FORMULAS" on page 75.
Timer B input (Pulse width measurement mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time (Note) TBiIN input high-level pulse width (Note) TBiIN input low-level pulse width (Note) Parameter Limits Min. 320 160 160 Max. Unit ns ns ns
Note. Limits change depending on f(XIN). Refer to "DATA FORMULAS" on page 75.
A-D trigger input
Symbol tc(AD) tw(ADL)
____ ____
Parameter
ADTRG input cycle time (minimum allowable trigger) ____ ADTRG input low-level pulse width
Limits Min. 1000 125 Max.
Unit ns ns
Serial I/O
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input high-level pulse width CLKi input low-level pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time
______ ___
Parameter
Limits Min. 200 100 100 0 30 90 Max.
Unit ns ns ns ns ns ns ns
80
External interrupt INTi input, key input interrupt KIi input
Symbol tw(INH) tw(INL) tw(KIL)
INTi input high-level pulse width ___ INTi input low-level pulse width __ KIi input low-level pulse width
___
Parameter
Limits Min. 250 250 250 Max.
Unit ns ns ns
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DATA FORMULAS Timer A input (Gating input in timer mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Limits Min. 8 ! 109 2 * f(f2) 4 ! 109 2 * f(f2) 4 ! 109 2 * f(f2) Max. Unit ns ns ns
Timer A input (External trigger input in one-shot pulse mode)
Symbol tc(TA) TAiIN input cycle time Parameter Limits Min. 8 ! 109 2 * f(f2) Max. Unit ns
Timer B input (In pulse period measurement mode or pulse width measurement mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width Parameter Limits Min. 8 ! 109 2 * f(f2) 4 ! 109 2 * f(f2) 4 ! 109 2 * f(f2) Max. Unit ns ns ns
Note. f(f2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 10.
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SWITCHING CHARACTERISTICS (VCC = 5 V 10%, VSS = 0 V, Ta = -20 to 85C, f(XIN) = 25 MHz (Note), unless otherwise noted)
Symbol td(E-P0Q) td(E-P1Q) td(E-P2Q) td(E-P3Q) td(E-P4Q) td(E-P5Q) td(E-P6Q) td(E-P7Q) td(E-P8Q) td(E-P9Q) td(E-P10Q) Parameter Test conditions Limits Min. Max. 80 80 80 80 80 80 80 80 80 80 80 Unit ns ns ns ns ns ns ns ns ns ns ns Port P0 data output delay time Port P1 data output delay time Port P2 data output delay time Port P3 data output delay time Port P4 data output delay time Fig. 74 Port P5 data output delay time Port P6 data output delay time Port P7 data output delay time Port P8 data output delay time Port P9 data output delay time Port P10 data output delay time Note. This applies when the main clock division selection bit = "0" and f(f2) = 12.5 MHz.
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10
1 E
50 pF
Fig. 74 Measuring circuit for ports P0 - P10 and
1
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
[External bus mode A] Memory expansion mode and microprocessor mode
(VCC = 5 V 10%, VSS = 0 V, Ta = 25 C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) Symbol td(An-E) Address output delay time Parameter Test (Note 2) Wait mode conditions No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 Limits Min. 12 87 12 75 18 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 22 57 5 45 9 15 Fig. 74 4 10 45 No wait Wait 1 Wait 0 18 50 130 5 20 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 12 87 12 87 18 18 0 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
td(A-E)
Address output delay time Address hold time ALE pulse width
th(E-An) tw(ALE)
tsu(A-ALE)
Address output setup time
th(ALE-A)
Address hold time
td(ALE-E) td(E-DQ) th(E-DQ) tw(EL) tpxz(E-DZ) tpzx(E-DZ) td(BHE-E)
ALE output delay time Data output delay time Data hold delay time
_
E pulse width
Floating start delay time Floating release delay time
___
BHE output delay time
_
td(R/W-E) th(E-BHE) th(E-R/W) td(E- 1) td( 1-HLDA)
R/W output delay time
BHE hold time _
____ ___
R/W hold time 1 output delay time HLDA output delay time
18 50
Notes 1. This applies when the main clock division selection bit = "0" and f(f2) = 12.5 MHz. 2. No wait : Wait bit = "1". Wait 1 : The external memory area is accessed with wait bit = "0" and wait selection bit = "1". Wait 0 : The external memory area is accessed with wait bit = "0" and wait selection bit = "0".
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
[External bus mode A] Memory expansion mode and microprocessor mode Bus timing data formulas (VCC = 5 V 10%, VSS = 0 V, Ta = -20 to 85 C,
Symbol Parameter f(XIN) = 25 MHz (Max., Note), unless otherwise noted) Limits Min. 1 ! 109 - 28 2 * f(f2) 9 3 ! 10 - 33 2 * f(f2) 1 ! 109 - 28 2 * f(f2) 9 3 ! 10 - 45 2 * f(f2) 9 1 ! 10 - 22 2 * f(f2) 9 1 ! 10 - 18 2 * f(f2) 9 2 ! 10 - 23 2 * f(f2) 1 ! 109 - 35 2 * f(f2) 9 2 ! 10 - 35 2 * f(f2) 9 1 ! 10 2 * f(f2)
9
td(An-E)
Address output delay time
Wait mode No wait Wait 1 Wait 0 No wait Wait 1 Wait 0
Max.
Unit ns ns ns ns ns ns ns ns ns ns
td(A-E)
Address output delay time
th(E-An)
Address hold time No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0
tw(ALE)
ALE pulse width
tsu(A-ALE)
Address output setup time
th(ALE-A)
Address hold time
- 25
ns ns
4 1 ! 109 2 * f(f2) 1 ! 109 2 * f(f2) 2 ! 109 2 * f(f2) 4 ! 109 2 * f(f2) 1 ! 109 2 * f(f2) 1 ! 109 2 * f(f2) 3 ! 109 2 * f(f2) 1 ! 109 2 * f(f2) 3 ! 109 2 * f(f2) 1 ! 109 2 * f(f2) 1 ! 109 2 * f(f2) 0 - 30 45 - 22 - 30 - 30 5 - 20 - 28 - 33 - 28 - 33 - 22 - 22 18
td(ALE-E)
ALE output delay time
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
td(E-DQ) th(E-DQ)
Data output delay time Data hold time
_
No wait Wait 1 Wait 0
tw(EL) tpxz(E-DZ) tpzx(E-DZ)
E pulse width
Floating start delay time Floating release delay time
___
td(BHE-E)
BHE output delay time
No wait Wait 1 Wait 0
_
td(R/W-E)
R/W output delay time
___
No wait Wait 1 Wait 0
th(E-BHE) th(E-R/W) td(E-
1)
BHE hold time
_
R/W hold time
1
output delay time
Notes 1. This applies when the main-clock division selection bit = "0". 2. f(f2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 10.
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NA IMI
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
[External bus mode B] Memory expansion mode and microprocessor mode
(VCC = 5 V 10%, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) Symbol td(CS-WE) td(CS-RDE) th(WE-CS) th(RDE-CS) td(An-WE) td(An-RDE) td(A-WE) td(A-RDE) th(WE-An) th(RDE-An) tw(ALE) Chip-select output delay time Parameter Test (Note 2) Wait mode conditions No wait Wait 1 Wait 0 Limits Min. 12 87 4 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 12 87 12 75 18 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 22 57 Fig. 73 5 45 9 15 4 10 45 No wait Wait 1 Wait 0 18 50 130 5 No wait Wait 1 Wait 0 20 48 128 10 0 0 18 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Chip-select hold time Address output delay time
Address output delay time Address hold time ALE pulse width
tsu(A-ALE)
Address output setup time
th(ALE-A)
Address hold time
td(ALE-WE) td(ALE-RDE) td(WE-DQ) th(WE-DQ) tw(WE) tpxz(RDE-DZ) tpzx(RDE-DZ) tw(RDE)
ALE output delay time Data output delay time Data hold delay time
___ ___
WEL/WEH pulse width
Floating start delay time Floating release delay time
___
RDE pulse width
____
td(RSMP-WE) td(RSMP-RDE) RSMP output delay time ____ th( 1-RSMP) RSMP hold time td(WE- 1) 1 output delay time td(RDE- 1) ____ td( 1-HLDA) HLDA output delay time Notes 1. This applies when the main clock division selection bit = "0" and f(f2) = 12.5 MHz. 2. No wait : Wait bit = "1". Wait 1 : The external memory area is accessed with wait bit = "0" and wait selection bit = "1". Wait 0 : The external memory area is accessed with wait bit = "0" and wait selection bit = "0".
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IN
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
[External bus mode B] Memory expansion mode and microprocessor mode Bus timing data formulas (VCC = 5 V 10%, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz (Max., Note1), unless otherwise noted)
Symbol td(CS-WE) td(CS-RDE) th(WE-CS) th(RDE-CS) td(An-WE) td(An-RDE) Parameter Wait mode No wait Wait 1 Wait 0 Chip-select hold time No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 Address hold time No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 td(ALE-WE) td(ALE-RDE) td(WE-DQ) th(WE-DQ) No wait Wait 1 Wait 0 Data output delay time Data hold time
___ ___
Chip-select output delay time
Limits Min. 1 ! 109 - 28 2 * f(f2) 9 3 ! 10 - 33 2 * f(f2) 4 1 ! 109 2 * f(f2) 3 ! 109 2 * f(f2) 1 ! 109 2 * f(f2) 3 ! 109 2 * f(f2) 1 ! 109 2 * f(f2) 1 ! 109 2 * f(f2) 2 ! 109 2 * f(f2) 1 ! 109 2 * f(f2) 2 ! 109 2 * f(f2) 9 1 ! 109 2 * f(f2) 4 1 ! 10 2 * f(f2)
9
Max.
Unit ns ns ns
- 28 - 33 - 28 - 45 - 22 - 18 - 23 - 35 - 35
ns ns ns ns ns ns ns ns ns ns
Address output delay time
td(A-WE) td(A-RDE) th(WE-An) th(RDE-An) tw(ALE)
Address output delay time
ALE pulse width
tsu(A-ALE)
Address output setup time
th(ALE-A)
Address hold time
- 25
ns ns
ALE output delay time
- 30 45
ns ns ns ns ns 5 ns ns ns ns ns ns 18 ns
No wait Wait 1 Wait 0
tw(WE) tpxz(RDE-DZ) tpzx(RDE-DZ)
WEL/WEH pulse width
1 ! 109 2 * f(f2) 2 ! 109 2 * f(f2) 4 ! 109 2 * f(f2) 1 ! 109 2 * f(f2) 2 ! 109 2 * f(f2) 4 ! 109 2 * f(f2) 1 ! 109 2 * f(f2) 0 0
- 22 - 30 - 30
Floating start delay time Floating release delay time
___
- 20 - 32 - 32 - 30
No wait Wait 1 Wait 0
tw(RDE) td(RSMP-WE) td(RSMP-RDE) th( 1-RSMP) td(WE- 1) td(RDE- 1)
RDE pulse width
____
RSMP output delay time
____
RSMP hold time
1
output delay time
Notes 1. This applies when the main-clock division selection bit = "0". 2. f(f2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 10.
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TIMING DIAGRAM
tr tf tc
Single-chip mode
XIN
tw(H)
tw(L)
E
td(E-PiQ)
Port Pi output (i = 0 - 10) Port Pi input (i = 0 - 8, 10)
tsu(PiD-E)
th(E-PiD)
td(E-P1Q)
Port P1 output
tsu(P1D-E)
Port P1 input
th(E-P1D)
td(E-P2Q)
Port P2 output
tsu(P2D-E)
Port P2 input
th(E-P2D)
td(E-P3Q)
Port P3 output
tsu(P3D-E)
Port P3 input
th(E-P3D)
td(E-P4Q)
Port P4 output
tsu(P4D-E)
Port P4 input
th(E-P4D)
td(E-P5Q)
Port P5 output
tsu(P5D-E)
Port P5 input
th(E-P5D)
td(E-P6Q)
Port P6 output
tsu(P6D-E)
Port P6 input
th(E-P6D)
td(E-P7Q)
Port P7 output
tsu(P7D-E)
Port P7 input
th(E-P7D)
td(E-P8Q)
Port P8 output
tsu(P8D-E)
Port P8 input
th(E-P8D)
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
tc(TA) tw(TAH) TAiIN input
tw(TAL)
tc(UP) tw(UPH) TAiOUT input tw(UPL)
In event count mode
TAiOUT input (Up-down input) TAiIN input (when count by falling) TAiIN input (when count by rising)
th(TIN-UP)
tsu(UP-TIN)
In event counter mode (When two-phase pulse input is selected) TAjIN input
tsu(TAjIN-TAjOUT)
tc(TA)
tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN)
TAjOUT input
tsu(TAjOUT-TAjIN)
tc(TB) tw(TBH) TBiIN input tw(TBL)
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
tc(AD) tw(ADL)
ADTRG input
tc(CK) tw(CKH) CLKi
tw(CKL)
th(C-Q) TxDi td(C-Q) RxDi tSU(D-C) th(C-D)
tw(INL)
INTi input Kli input
tw(INH) tw(KNL)
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory expansion mode and microprocessor mode (When wait bit = "1")
1
E or RDE, WEL, WEH
RDY input
tsu(RDY-
1)
th(
1-RDY)
( When wait bit = "0")
1
E or RDE, WEL, WEH
RDY input
tsu(RDY-
1)
th(
1-RDY)
(When wait bit = "1" or "0" in common)
1
tsu(HOLD-
HOLD input
1)
th(
1-HOLD)
td(
HLDA output
1-HLDA)
td(
1-HLDA)
Test conditions * VCC = 5 V 10% * Input timing voltage : V IL = 1.0 V, VIH = 4.0 V * Output timing voltage : V OL = 0.8 V, VOH = 2.0 V
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
[External bus mode A]
Memory expansion mode and microprocessor mode (No wait : When wait bit = "1")
tw(L)
tw(H)
tf
tr
tc
XIN
1
td(E- 1) tw(EL) E
td(E- 1)
td(An-E)
th(E-An) Address Address Address
An
tw(ALE)
td(ALE-E)
ALE
th(ALE-A) tsu(A-ALE) th(E-DQ) tpxz(E-DZ) tpzx(E-DZ)
Am/Dm
Address
Data
Address th(E-D) tsu(D-E) Data
Address
td(E-DQ) td(A-E)
DmIN
th(E-BHE)
td(BHE-E) BHE
td(R/W-E)
th(E-R/W)
R/W
Test conditions * VCC = 5 V 10% * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V * Data input DmIN : VIL = 0.8 V, VIH = 2.5 V
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
[External bus mode A]
Memory expansion mode and microprocessor mode (Wait 1 : The external area is accessed when wait bit = "0" and wait selection = "1".)
tw(L) XIN
tw(H)
tf tr
tc
1
td(E-
E
1)
td(E- tw(EL)
1)
td(An-E) An
th(E-An) Address Address
tw(ALE) ALE
td(ALE-E)
th(ALE-A) tsu(A-ALE) Am/Dm Address Data th(E-DQ) tpxz(E-DZ) Address tpzx(E-DZ) Address
td(A-E)
td(E-DQ) tsu(D-E)
th(E-D)
DmIN
Data td(BHE-E) th(E-BHE)
BHE
td(R/W-E) R/W
th(E-R/W)
Test conditions * Vcc = 5 V 10% * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V * Data input DmIN : VIL = 0.8 V, VIH = 2.5 V
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
[External bus mode A]
Memory expansion mode and microprocessor mode (Wait 0 : The external memory area is accessed when wait bit = "0" and wait selection bit = "0".)
tw(L) XIN
tw(H)
tf tr
tc
1
td(E-
E
1)
td(E- tw(EL)
1)
td(An-E) An Address
th(E-An) Address Address
tw(ALE) ALE
td(ALE-E)
tsu(A-ALE)
th(ALE-A) th(E-DQ) tpxz(E-DZ) Address tpzx(E-DZ) Address
Am/Dm
Address td(A-E)
Data td(E-DQ)
tsu(D-E) DmIN th(E-BHE) Data
th(E-D)
td(BHE-E)
BHE
td(R/W-E) R/W
th(E-R/W)
Test conditions * Vcc = 5 V 10% * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V * Data input DmIN : VIL = 0.8 V, VIH = 2.5 V
87
PR
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MI ELI
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
[External bus mode B]
Memory expansion mode and microprocessor mode (No wait : When wait bit = "1")
tw(L)
tw(H)
tf
tr
tc
XIN
1
td(WE-
1)
td(WE-
1)
td(RDE-
1)
td(RDE-
1)
CS0 - CS4 td(CS-WE) th(WE-CS) td(CS-RDE) th(RDE-CS)
An
td(An-WE) tw(ALE)
Address
td(An-RDE) td(ALE-WE) th(WE-An)
Address
Address
th(RDE-An)
ALE
th(ALE-A) tsu(A-ALE) th(WE-DQ) tpxz(RDE-DZ) tpzx(RDE-DZ) td(ALE-RDE)
Am/Dm
Address
Data
Address
td(A-RDE)
Address
td(WE-DQ) td(A-WE) tw(WE) WEL, WEH
th(RDE-D) tsu(D-RDE)
DmIN
Data
tw(RDE)
RDE th( td(RSMP-WE)
1-RSMP)
td(RSMP-RDE)
RSMP
Test conditions * Vcc = 5 V 10% * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V * Data input DmIN : VIL = 0.8 V, VIH = 2.5 V
88
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NA
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
[External bus mode B]
Memory expansion mode and microprocessor mode (Wait 1 : The external area is accessed when wait bit = "0" and wait selection bit = "1".)
tw(L) XIN
tw(H)
tf tr
tc
1
td(WE-
CS0 - CS4
1)
td(WE-
1)
td(RDE- td(RDE1)
1)
th(WE-CS) td(CS-RDE) td(CS-WE) An td(An-WE) tw(ALE) ALE th(ALE-A) tsu(A-ALE) Am/Dm Address Data td(ALE-RDE) th(WE-DQ) tpxz(RDE-DZ) tpzx(RDE-DZ) Address Address Address td(An-RDE) td(ALE-WE) th(WE-An) th(RDE-An) th(RDE-CS)
Address
td(A-WE)
td(WE-DQ) tw(WE)
td(A-RDE)
WEL, WEH
th(RDE-D) tsu(D-RDE) Data
DmIN
tw(RDE)
RDE
th(
RSMP
1-RSMP)
td(RSMP-WE)
td(RSMP-RDE)
Test conditions * Vcc = 5 V 10% * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V * Data input DmIN : VIL = 0.8 V, VIH = 2.5 V
89
PR
. . tion nge ifica to cha t pec al s subjec fin re a ot a is n limits This ric ice: aramet Not e p Som
MI ELI
NA
RY
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
[External bus mode B]
Memory expansion mode and microprocessor mode (Wait 0 : The external memory area is accessed when wait bit = "0" and wait selection bit = "0".)
tw(L) XIN
tw(H)
tf tr
tc
1
td(WE-
1)
td(WE-
1)
td(RDE-
1)
td(RDE-
1)
CS0 - CS4
td(CS-WE)
th(WE-CS)
td(CS-RDE) th(RDE-CS)
An td(An-WE) tw(ALE) ALE
Address td(An-RDE) td(ALE-WE) th(WE-An)
Address
Address
th(RDE-An)
td(ALE-RDE) tsu(A-ALE)
th(ALE-A)
th(WE-DQ) Address td(A-RDE)
tpxz(RDE-DZ)
tpzx(RDE-DZ) Address
Am/Dm
Address td(A-WE)
Data td(WE-DQ)
tw(WE)
WEL, WEH
tsu(D-RDE) Data
th(RDE-D)
DmIN
tw(RDE)
RDE
td(RSMP-WE)
RSMP
th(
1-RSMP)
td(RSMP-RDE)
Test conditions * Vcc = 5 V 10% * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V * Data input DmIN : VIL = 0.8 V, VIH = 2.5 V
90
PR
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
91
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IM REL
IN
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MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
* Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
*
* *
*
(c) 1996 MITSUBISHI ELECTRIC CORP. H-LF457-A KI-9611 Printed in Japan (ROD) New publication, effective Nov. 1996. Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev. No. 1.00 2.00 First Edition The following are revised:
Page P4 P100 - P107
P100 - P107 EVL0, EVL1 Output port P10 - I/O Output
M37736MHBXXXGP Datasheet
Revision Description Rev. date 970507 980731
Previous Version
In addition to having the same functions as port P0 in the single-chip mode, P104 - P107 also function as input pins for key input interrupt input (KI0 - KI3). These pins should be left open.
Revised Version
P100 - P107 EVL0, EVL1
I/O port P10 -
I/O Output
In addition to having the same functions as port P0 in the single-chip mode, P104 - P107 also function as input pins for key input interrupt input (KI0 - KI3). These pins should be left open.
P5 Right column Line 7
Previous Version Additionally, the internal ROM area can be modified by software.
Revised Version Additionally, the internal ROM and RAM area can be modified by software.
P5 Fig. 1
Notes 1. Internal ROM area can be modified. (Refer to the section on ROM area modification function.) The CPU operates on an internal clock 's frequency which is obtained by dividing the external clock frequency f(XIN) by two. The internal ROM size and its address area of the M37736MHBXXXGP can be modified by the memory allocation control register's bits 0,1 and 2 shown in Figure 71. Figure 73 shows the memory allocation in which the internal ROM size and its address area are modified. Memory allocation selection bits ROM size (ROM area) 0 0 0 : 124 Kbytes (addresses 00100016 - 01FFFF16) 0 0 1 : 120 Kbytes (addresses 00200016 - 01FFFF16) 1 1 0 : 96 Kbytes (addresses 00800016 - 01FFFF16) 1 1 1 : 32 Kbytes (addresses 00800016 - 00FFFF16)
Notes 1. Internal ROM and RAM area can be modified. (Refer to the section on ROM area modification function.) The CPU operates on an internal clock 's frequency.
P9 Right column Line 12 P66 Left column Line 2
The internal ROM size and RAM size of the M37736MHBXXXGP can be modified by the memory allocation control register's bits 0,1 and 2 shown in Figure 71. Figure 73 shows the memory allocation in which the internal ROM size and RAM size are modified.
P66 Fig.71
Memory allocation selection bits ROM size RAM size 0 0 0 : 124 Kbytes 3968 bytes 0 0 1 : 120 Kbytes 3968 bytes 0 1 0 : 60 Kbytes 2048 bytes 1 0 0 : 32 Kbytes 2048 bytes 1 0 1 : 16 Kbytes 2048 bytes 1 1 0 : 96 Kbytes 3968 bytes
P67 Fig. 73 P68 Right column Line 2
Refer to page (2). The M37736MHBXXXGP has 28 powerful addressing modes. Refer to the SINGLE-CHIP 16BIT MICROCOMPUTERS DATA BOOK for the details of each addressing mode.
Refer to page (3). The M37736MHBXXXGP has 28 powerful addressing modes. Refer to the "7700 Family Software Manual" for the details.
MACHINE INSTRUCTION LIST MACHINE INSTRUCTION LIST
The M37736MHBXXXGP has 103 machine instructions. Refer to the SINGLE-CHIP 16-BIT MICROCOMPUTERS DATA BOOK for details. The M37736MHBXXXGP has 103 machine instructions. Refer to the "7700 Family Software Manual" for the details.
(1)
REVISION DESCRIPTION LIST
M37736MHBXXXGP Datasheet
Previous version
(ML2, ML1, ML0) = (0, 0, 0)
ROM size : 124 Kbytes
(ML2, ML1, ML0) = (0, 0, 1)
ROM size :120 Kbytes
(ML2, ML1, ML0) = (1, 1, 0)
ROM size : 96 Kbytes
(ML2, ML1, ML0) = (1, 1, 1)
ROM size : 32 Kbytes
00000016 00007F16 00008016 000FFF16 00100016
SFR Internal RAM 3968 bytes
00000016 00007F16 00008016 000FFF16 00200016
SFR Internal RAM 3968 bytes
(4 Kbytes)
00000016 00007F16 00008016 000FFF16
SFR Internal RAM 3968 bytes (28 Kbytes)
00000016 00007F16 00008016 000FFF16
SFR Internal RAM 3968 bytes (28 Kbytes)
Internal ROM 60 Kbytes
Internal ROM 56 Kbytes
00800016 Internal ROM 32 Kbytes
00800016 Internal ROM 32 Kbytes 00FFFF16 01000016
00FFFF16 01000016
00FFFF16 01000016
00FFFF16 01000016
Internal ROM 64 Kbytes
Internal ROM 64 Kbytes
Internal ROM 64 Kbytes
01FFFF16
01FFFF16
01FFFF16
FFFFFF16
FFFFFF16 : External memory area
FFFFFF16
FFFFFF16
Note. In the external bus mode B, bank 1016-FF16 cannot be accessed.
Fig. 73 Memory allocation (modification of internal ROM area by memory allocation selection bit)
(2)
REVISION DESCRIPTION LIST
M37736MHBXXXGP Datasheet
Revised version (ML2, ML1, ML0) = (0, 0, 0) 00000016 00007F16 00008016 000FFF16 00100016 SFR Internal RAM 3968 bytes (ML2, ML1, ML0) = (0, 0, 1) 00000016 00007F16 00008016 000FFF16 00200016 SFR Internal RAM 3968 bytes
(4 Kbytes)
(ML2, ML1, ML0) = (0, 1, 0) 00000016 00007F16 00008016 00087F16 00100016 Internal ROM 60 Kbytes 00FFFF16 01000016 SFR Internal RAM 2048 bytes
(1.9 Kbytes)
00FFFF16 01000016
Internal ROM 124 Kbytes
00FFFF16 01000016
Internal ROM 120 Kbytes
01FFFF16
01FFFF16
FFFFFF16
FFFFFF16
FFFFFF16
(ML2, ML1, ML0) = (1, 0, 0) 00000016 00007F16 00008016 00087F16 SFR Internal RAM 2048 bytes (29.9 Kbytes) 00800016 Internal ROM 32 Kbytes 00FFFF16 01000016
(ML2, ML1, ML0) = (1, 0, 1) 00000016 00007F16 00008016 00087F16 SFR Internal RAM 2048 bytes (45.9 Kbytes)
(ML2, ML1, ML0) = (1, 1, 0) 00000016 00007F16 00008016 000FFF16 00800016 SFR Internal RAM 3968 bytes (28 Kbytes)
00C00016 00FFFF16 01000016
Internal ROM 16 Kbytes
00FFFF16 01000016
Internal ROM 96 Kbytes
01FFFF16
FFFFFF16
FFFFFF16
FFFFFF16
: External memory area Note. In the external bus mode B, bank 1016-FF16 cannot be accessed. Fig. 73 Memory allocation (modification of internal ROM and RAM area by memory allocation selection bits)
(3)
REVISION DESCRIPTION LIST
Rev. No. 2.00
Page P67 Table 12
Memory allocation selection bits ML1 ML0 ML2 0 0 1 1 0 0 1 1 0 1 0 1 Internal ROM area 00100016 - 01FFFF16 00200016 - 01FFFF16 00800016 - 01FFFF16 00800016 - 00FFFF16
M37736MHBXXXGP Datasheet
Revision Description
Previous Version
Rev. date 980731
Access address CS0 ------------ 00100016 - 001FFF16 00100016 - 007FFF16 00100016 - 007FFF16 CS1 02000016 - 03FFFF16 02000016 - 03FFFF16 02000016 - 03FFFF16 01000016 - 03FFFF16
Revised Version
Memory allocation selection bits ML1 ML0 ML2 0 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 0
Internal ROM area 00100016 - 01FFFF16 00200016 - 01FFFF16 00100016 - 00FFFF16 00800016 - 00FFFF16 00C00016 - 00FFFF16 00800016 - 01FFFF16
Access address CS0 CS1 02000016 - 03FFFF16 ------------ 02000016 - 03FFFF16 00100016 - 001FFF16 00088016 - 000FFF16 01000016 - 03FFFF16 00088016 - 007FFF16 01000016 - 03FFFF16 00800016 - 00BFFF16 00088016 - 007FFF16 01000016 - 03FFFF16 00100016 - 007FFF16 02000016 - 03FFFF16
P90 [External bus mode B]
Previous Version
[External bus mode B]
Memory expansion mode and microprocessor mode (Wait 0 : The external memory area is accessed when wait bit = "0" and wait selection bit = "1".)
Revised Version
[External bus mode B]
Memory expansion mode and microprocessor mode (Wait 0 : The external memory area is accessed when wait bit = "0" and wait selection bit = "0".)
(4)

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